As semiconductor feature sizes continue to shrink, the challenges to functionally verify designs using this advanced technology are also increasing. Gone are the days of simple gate-level or RTL simulation. These next-generation chips are composed of multiple CPU cores, DSPs and specialized function blocks all the while interfacing to multiple protocols and often packaged for portable use.

With so much more being offered by the design engineering community in terms of chip capacity, the verification engineering community has required advances in their ability to ensure working silicon with no or few re-spins. It has been noted in many research reports that verification has become the bottleneck for design.

Accellera was keenly aware verification was going to be an ever-increasing challenge for design that it created SystemVerilog (IEEE-1800) by augmenting Verilog with advanced verification features to facilitate testbench automation, assertion based verification (ABV) and coverage driven verification (CDV). The language enhancements in SystemVerilog could be easily adopted since traditional Verilog tools and current hardware implementation flows were augmented, not changed. While SystemVerilog boosts productivity in design and validation, its standardized definition of assertions has ushered in the era of formal assertion-based verification flows that support .

With the uptake in use of SystemVerilog, the verification community has discovered additional standardization needs. Accellera is working on two that have come from the uptake in SystemVerilog usage. Those two Accellera Technical Subcommittees are the Unified Coverage Interoperability Standard (UCIS) and Verification IP (VIP) groups.

The UCIS group was created out of the need to manage the voluminous amounts of information that are generated during the verification process from numerous different types of applications. The goal of the group is to define a standard application programming interface (API) that tool providers and users can employ to manage verification results. In the absence of a standard, each tool supplier offers their own scheme to access and manage information and each user community develops interface programs to manage the information. While SystemVerilog made the verification testbench and assertions portable, it did not make the results from verification as portable. UCIS is a key element to promote verification results portability for the user.