Chip and system developers once considered verification as a secondary activity following the main challenge of design, with the "Designer" playing the central role in a design's success. This notion is firmly turned on its head today, as verification is the biggest component of chip hardware development budgets, schedules, staffing and risk.

With verification complexity growing faster than Moore's Law, compounded by increasing mixed-signal content and advanced low-power design techniques, the importance of verification in the chip hardware development process is certain to increase. In fact, venture capitalists have started focusing on verification costs as a factor in determining which chip startups to fund. Similarly, embedded software used to be a minor or nonexistent deliverable for typical semiconductor devices. At 45 nm and beyond, software accounts for a full 60 percent of total chip-development cost, with major implications on how chips and systems are verified. It is no surprise, then, that the International Technology Roadmap for Semiconductors (ITRS) predicts that, "Without major breakthroughs, verification will be a non-scalable, show-stopping barrier to further progress in the semiconductor industry."

The growing role of verification complexity and embedded software in the chip-development process presents many challenges to tool vendors and system designers alike. The four areas that vendors and designers must focus on to address key software-to-silicon verification challenges are:

• Verification efficiency.

• Verification performance.

• Early software development.

• Cross-domain verification.

Efficiency and performance
Chips have become almost unimaginably complex, with dozens of interacting embedded processor cores, accelerators, complex on-chip buses and high-speed external interfaces. This underlying chip complexity poses a major problem for system developers regarding how to sufficiently exercise the effectively infinite state space within a reasonable time, to find bugs that will cause costly respins or potentially kill their chips. The reasons for the exploding verification state space are well known: these designs include pervasive use of advanced power management techniques, tighter integration of analog/mixed-signal components with the digital functions and large amounts of software.