Traditionally, CMOS downscaling has had the double benefit of increasing device performances and reducing power consumption. This trend has, however, reached its limits. The devices' copper interconnects are introducing problems of crosstalk, power consumption and resistive-capacitive delay.

Meanwhile, the motivations for going into the third dimension have increased since the technology achieves smaller form factor with increased package densities to meet bandwidth, radiofrequency, power consumption performance improvements while keeping cost reduction targets. Through-Silicon-Via (TSV) wafers have the potential to represent as much as 25 percent of the memory business by 2015.

The Electronics and Information Technology Laboratory of the CEA (CEA-Leti), which hosted the workshop, has envisaged a nanowire-based architecture for sub-22nm gate length transistors. At the Leti Annual Review Meeting held in mid-June Thomas Ernst, CEA-Leti senior scientist, presented a 3-D-stacked nanowire technology for MOSFETs and memories.

"Developing a nanowire technology consists of optimizing the architecture to convert what is considered as parasitic in a full planar technology into an advantage in a semi 3-D or full 3-D device," Ernst told EE Times.

"Introducing two additional lateral gates to reduce the leakage currents is very effective. But this should not penalize the global density of the circuit. This is why the technological choices should not be done on individual devices but on small circuits. CEA-Leti's 300-mm facilities and our work in the STMicroelectronics-IBM Alliance enabled us to evaluate those technologies within industrial constraints."

Ernst explained that 3-D multilevel nanowires, or more generally multichannels, are very effective at maximizing surface area in a minimum of space. This can be used to increase the current drive of a multichannel technology, or to increase the surface for charge trapping in a flash-memory technology. He declared: "We measured a huge gain in current up to a factor 7 compared to the planar case thanks to the 3-D configuration. When the levels are disconnected, real 3-D devices can be imagined."

Leti's 3D flash memory concept