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Analysis: Intel slowly gears up for system-on-chips
Industry yet to feel impact of changes inside PC giant
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EE Times


SAN JOSE, Calif. — Intel Corp. isn't giving much detail on its two-year old initiative to become a systems-on-chip supplier. But interviews with executives and analysts show the company is making gradual progress laying the foundations to build competitive SoCs for cellphones, TVs, videogame consoles and communications gear.

The initiative strategically opens up whole new markets for Intel beyond its maturing PC business. But it requires new tools and skills for the company, and it puts Intel into direct competition with ARM Ltd., IBM Corp., MIPS Technologies and the long list of well-established embedded chip makers using those company's cores.

The x86 giant's first crop of SoCs so far has failed to gain any design wins among top tier OEMs. Nevertheless, Intel has made strides developing the process technology, design tools, interconnect strategy and silicon blocks it needs to become a significant player.

In a series of interviews, Intel execs sketched out the company's progress to date. They were most specific in the area of the company's greatest strength—process technology.

Intel has completed work on a low power version of its 45nm process geared for making SoCs and it will have a 32nm version available for its chip designers to use next year. Going forward, the company plans to develop separate versions of its process technology for high performance PC processors and low power SoCs, including 22nm versions already in the works.

In addition to the high performance transistors used for PC processors, the SoC process also offers transistors that have 10 to 1,000 times less power leakage. However, the thicker oxide layers on those circuits reduce their performance by a factor of three.

"That's a pretty good trade off," said Mark Bohr, an Intel senior fellow of logic technology development.

Intel's senior fellow of logic technology development
Mark Bohr

The SoC process also supports a wider range of high voltage I/Os, up to 3.3V, to interface with older silicon blocks and NAND memory. In addition, it includes a library of high precision inductors, resistors, capacitors and varactors used in RF and other analog blocks.

"This suite of features is typically available in other SoC processes from other companies," said Bohr. "What makes us unique is we can do it with high-k metal gate transistors to get down to really low leakage," factors that help support low power and high voltage operations, he added.

Metal finger capacitors (left) and inductors (right).

In addition, SoC designers can also use the high performance transistors geared for PC processors. The SoC process "gives us an excellent combination of performance with low active and leakage power, said Gadi Singer, a veteran Intel exec driving the corporate SoC initiative quietly launched in mid-2007.

Creating the low power version of the process requires "a very small incremental cost," Bohr said.

Intel has 14 SoCs now in development that will use its 32nm low power process (called P1269) now being tested. The 45nm SoC process (P1266.8) has a subset of its features, and it is being used for products in pilot production now, including integrated mobile and TV processors called Lincroft and Sodaville, respectively.

Singer said the 32nm SoCs will use a common framework. It includes the new process technology, a "fabric" of Intel-defined on-chip interconnects, a new EDA flow with an SoC test methodology and a shared library of silicon blocks.



Page 2: Intel's Taiwan connection
Page 3: Interconnects for internal use only
Page 4: Intel's silicon library: no Alexandria
Page 5: Design wins: Waiting for Godot?

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Related Links:

  • Online course: Fundamentals of SoCs
  • AMD, Intel at it again, as both take aim at SoC
  • White paper: Memory challenges in high-end SoCs



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