A complement to Synopsys' TetraMAX diagnostics solution, Yield Explorer links all aspects of the design, manufacturing and test flows into a single data-bank and minimizes design re-spin through rapid and comprehensive capture of design-process-test interactions causing low yield, Synopsys said.

Yield Explorer's graphical user interface is structured around a layout viewer for superposition of test failures on the corresponding layers of physical design.

Faced with growing challenging production ramp at each nanometer node, Nvidia said it needed to consolidate all volume ramp activities in a single tool.

With Synopsys' Yield Explorer, Nvidia said it is able to coherently combine and cross-correlate large volumes of data from the design, fab and test domains to rapidly identify dominant failure mechanisms.

"We selected Yield Explorer because this solution has all the traditional yield analysis features combined with unique design-centric, volume diagnostics capabilities. Yield Explorer was able to handle gigabytes of data per day from the test floor and combine it with the design and fab data," commented Bruce Cory, DFT manager at Nvidia.

STMicroelectronics is another licensee of Synopsys' Yield Explorer, the company's spokesperson told EE Times.

Synopsys' spokesperson explained: "While we can't name any other Yield Explorer customers at this time, we can say that Yield Explorer has five ongoing evaluations with select target customers who stand to immediately benefit from Yield Explorer's design-centric yield analysis capabilities."

Synopsys' spokesperson added: "With our early success at STMicroelectronics as a springboard, we are seeing good follow through in terms of interest from EU companies."

In May, Nvidia adopted Synopsys' IC Validator for validating multi-billion transistor graphics processors and claimed they had achieved near-linear scalability, such as the 20x accelerated time to tapeout speedup using 25 CPUs.