"To logic synthesis people, the message is clear," said Madhavan. "Resistance is futile. You will be assimilated."

To reduce the cost of silicon as feature sizes shrink, Madhavan said, EDA vendors will need to provide automated RTL-to-GDSII design systems, not collections of individual tools. And for new process geometries, he said, most optimization decisions will need to be made during routing, well downstream from today's logic synthesis.

The cost of design is becoming prohibitive at 90 and 65 nm, Madhavan said. For each new process generation, he observed, the cost of engineering goes up 60 percent, the cost of manufacturing goes up 40 percent, and the non-recurring engineering (NRE) and mask costs go up by 100 percent.

"We pride ourselves on being electronic design automation, but we have become electronic design assistance," Madhavan said. "We provide a bunch of widgets that our customers have to put together."

Madhavan then discussed the history of logic synthesis, which he said hit a "middle age crisis" around 1995 when block sizes were limited and timing budgets were done manually. Further work was able to increase block sizes to 100,000 gates and automate time budgeting. But then, he said, logic synthesis began to move into "old age" with no physical knowledge, a netlist that couldn't be implemented, and timing that couldn't be achieved in layout.

Physical synthesis, which linked synthesis with placement, brought a "transfusion of energy into the old age of the technology," Madhavan said. But even that is no longer good enough. As yields become problematic, design rules multiply, and analysis becomes statistical, more and more decisions need to be made later in the process, he said.

It's no longer enough to just consider wire delays, Madhavan noted; switching between neighboring wires is now critical, and that can only be evaluated during routing. "Almost all optimization is migrating downstream," he said. "Decisions can only be made much further down the chain."

"It's time for a much more integrated platform from which we can alter the cost of design for our customers," Madhavan said. At 65 nm, he noted, design will move away from isolated domains to the "tall, thin VLSI designer," working in an environment in which there is no separation between "front end" and "back end" design.

"The way we've seen logic synthesis as a separate commodity has to end," Madhavan concluded. "We've got to be about automation, about cost control for customers, about getting customers to do more and more silicon."

ISPD 2005 runs April 3-6 in San Francisco, Calif.