San Francisco — The annual preview of coming attractions at the International Solid-State Circuits Conference, slated for today, will show a confab vastly changed from the days of ISSCC's singular focus on microprocessor speeds and memory-chip densities.

The record number of papers that will once again be presented at this landmark event, to be held here Feb. 5 to 9, will again topple records in chip density, performance and sophistication. But amid the sound of shattering records are more subtle themes: gradual shifts in architectural thinking, the quiet emergence of entirely new technologies in bioscience and organic circuits and the incredible continuity of silicon CMOS.

The CMOS theme will be sounded in the first keynote of the plenary session, when IBM fellow Tze-Chiang Chen will suggest that, contrary to the hype, CMOS will continue to serve the industry for at least another decade. Chen will cite problems that come with that longevity, including the much-discussed issues of power dissipation and process variations, but will conclude that CMOS designers will find ways — from new tools to self-healing, self-biasing circuits — to deliver systems.

Hermann Eul, member of the management board at Infineon Technologies AG, and Ken Kutaragi, president and CEO of Sony Computer Entertainment, will take up the same theme — Eul from the perspective of mobile multimedia and Kutaragi from that of interactive entertainment.

But the real fun, as always, will come in the technical sessions. Perhaps the most clear-cut signal of change at the conference will come in the processor section. It has been widely discussed — ever since Intel Corp. made it acceptable to say so in public — that the pursuit of uniprocessor performance is at an end. And this year, for the first time in ISSCC history, no single-core processors will be presented. Papers range from a dual-core Intel Xeon CPU to a RISC-based networking system-on-chip from Cavium Networks with 16 cores.

This is not to say that developers have given up on performance. A subsequent session will describe building blocks for future processor cores, including a speed-leading 9-GHz integer execution unit for the Pentium 4 architecture and a 10.1-GHz register file, both from Intel. Significantly, both designs are in 65-nanometer CMOS. Even more significantly, the register file is specifically architected to be resistant to expected process variations.

Variation resistance is just one of the strategies that will be discussed for dealing with the growing design and operational problems at fine geometries. A paper from Philips, for example, will describe an on-chip network of sensors — for voltage, temperature and signal integrity — linked by a scan chain to give near-real-time operating data on specific sites on a packaged chip. While the architecture is intended for debug purposes, it is easy to project its use for real-time performance optimization on chips that, if run open-loop, would fail.

Nor will the problems of huge multicore chips in advanced geometries be limited to temperature, voltage and process variations. The enormous appetite for data and instructions aggregated from those processors has exceeded the abilities of conventional memory and interconnect ideas, as a number of papers will indicate.

To aid in meeting the demand, on-chip Level 2 caches have grown into multimegabyte monsters. And in one case, the design includes a 16-Mbyte, 16-way set-associative L3 on the die.

At those speeds, I/O is clearly a problem as well. A Sun Microsystems Inc. eight-core Sparc design includes four DDR2 DRAM controllers in an effort to keep the beasts fed. At the system level, the problem will be even worse. The scale of the communications issue will be illustrated by a Fujitsu paper describing how a 1.333-Gbit/second I/O pin design is incorporated into a 10-chip backplane interconnect crossbar to yield an aggregate throughput in excess of 1 terabit/s.

If digital design is looking to more cores and faster everything, equally important moves are taking place in other areas. Data converters continue their gains in performance, and flash memory shows continually increasing density.

In one paper, one of the alternatives to traditional flash, multilevel nitrided read-only memory, or NROM, has been used by Israeli technology developer Saifun Semiconductors Ltd. and memory vendor Macronix International Co. Ltd. to produce a 4-bit/cell, 1-Gbit flash device for data storage applications.

Meanwhile, ISSCC will host a surprisingly well-populated session on organic devices. Other papers will describe the progress being made in printing important circuit building blocks — including whole CPUs, analog signal-processing elements and SRAMs — on flexible substrates. In one case, a 13.56-MHz RFID transponder has been printed on an organic substrate.

In bioelectronics, one remarkable example is a flip-chip combination of a mixed-signal ASIC and an electrode array intended to be implanted in the inner ears of guinea pigs. The ASIC communicates with the outside world and draws power via a wireless interface. It relays signals to the electrode chip, which directly stimulates the animal's auditory nerve. A denser device could potentially be used for hearing-impaired humans. Two papers each will describe DNA recognition chips, retinal-implant ICs and biosignal acquisition chips.