DALLAS Gate oxides are more robust than previously believed, leading to possibilities that chip designers may be able to push device speeds harder while remaining within acceptable reliability margins, said Ashraf Alam, a distinguished member of the technical staff at Agere Systems (Allentown, Pa.).
Speaking Monday (March 31) at the International Reliability Physics Symposium, Alam said a team at Agere Systems has concluded that at the lower voltages of today's products, soft breakdowns in both NMOS and PMOS transistors are less of a problem than previously thought.
For many years researchers have believed that PMOS transistors in particular were susceptible to soft breakdowns, the gradual worsening of device performance as small defects in the gate oxide caused current leakage.
Because the defects in oxides are almost completely random, they do not cluster in particular transistors. And as scaling progresses, the likelihood diminishes that the smaller transistors will have several defects in one spot - just as darts are unlikely to hit the smaller spots on a target.
The randomness of defects in silicon dioxide is "very surprising, because nothing in nature seems to have defects that are completely random. Lightning will tend to strike in one place, and then strike again and again in the same general area, for example," Alam said.
The likelihood that soft breakdowns will result in a chip failure are so small for leading-edge devices that companies practically can ignore the problem for well-designed and characterized devices "without fear of a product recall," he said.