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Researchers debate negative-bias effects on chips
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Austin, Texas - As transistor scaling continues apace, researchers are paying increasing attention to the effects of negative-bias temperature instability on circuit performance, and are reaching different conclusions from those studies.

Models created by an engineer at Agere Systems Inc. show that while NBTI has an increasing impact on circuit performance and reliability as scaling proceeds, self-healing techniques greatly reduce its effects. A team of Texas Instruments Inc. engineers argues, however, that it is nearly impossible to predict how individual circuits might benefit from self-healing.

NBTI can severely impact the speed of PMOS transistors after they are used for a long period, and has been a particularly devilish issue for companies making analog circuits. Though circuit designers take into account a standard process variation, NBTI introduces unpredictable timing delays that cause circuits to lose performance or fail to function.

NBTI degradation occurs when defects generated at the interface between the silicon dioxide and the channel tend to scatter the holes that carry charge in the PMOS transistors. These defects in the oxide interface "can take extra charges and shift the threshold voltage," said Souvik Mahapatra, a former Bell Labs researcher who now teaches at the India Institute of Technology in Mumbai (the former Bombay). "Headroom drops, as well as drive current."

The problem now is moving out to digital circuits as oxides are thinned to near the physical scaling limits.

According to the models created by Muhammed Alam, a distinguished engineer working at Agere Systems' facility in Allentown, Pa., the news about NBTI effects is both good and bad. Alam became well-known within the technical community several years ago for developing models that predicted that gate oxide scaling could proceed without major reliability concerns.

Alam does not minimize the NBTI issue, however. "The importance of the NBTI problem is major, and every large chip company is working on it." His simulations at Agere, as well as experimental data obtained from several large manufacturing companies, agree that NBTI worsens as scaling proceeds. "At the same time as we are making oxides thinner, we are increasing the speed of these devices," Alam said. "And it turns out that as we switch faster, we create these speed bumps, these defects in the oxide." However, "when the transistor turns itself off, it heals itself through annealing effects, repairing 60 percent of the damage," Alam said.

The off-state lasts only a few nanoseconds, depending on the frequency of the chip, but that is long enough for the healing effect to work its magic, he said.

When companies study NBTI, they usually leave the chips on all of the time, which Alam said is unrealistic. "As we go to higher speeds, there is a chance that because of this annealing effect, lifetime is going to last four to 10 times longer. It is possible to optimize the design and manufacturing to keep the circuit viable and keep scaling going," he concluded. Alam said his work shows "a coherent principle of how this recovery process takes place, and shows how everybody's data fits within a single framework."

Alam and the India Institute of Technology's Mahapatra argue that the shift from buried-channel devices to surface-channel devices to increase performance has caused the NBTI effect to increase, particularly for chips made with 130-nanometer and 90-nm design rules. Analog designers often want to keep operating voltages high, at 3.3 volts, while increasing performance by moving to a thinner oxide of 50 to 70 angstroms. "That is a bad combination," Mahapatra said.

Alam said that analog-centric companies have labored for many years to guard against NBTI effects in their circuit models. For digital circuits, "it is an upcoming problem. National Semiconductor and other analog companies have been way ahead of others in figuring NBTI effects into their designs. Now, even those without analog products are writing papers about it, discovering that some parts of the circuit may be more sensitive to certain amounts of shift."

At Texas Instruments, a team of engineers looking at mobility degradation from NBTI downplayed the importance of the recovery effect cited by Alam, and said chip companies are well-advised to develop more comprehensive circuit models to guard against NBTI.

Anand Krishnan and Srikanth Krishnan, both reliability engineers at Texas Instruments, also said their group was among the first to find the recovery effect upon which Alam has based his arguments.

"We do find annealing effects, and we know that recovery happens," Anand Krishnan said. "But from an overall perspective, it is very hard to capture the benefits of recovery at a system level because it is very hard to find out if this transistor is going to switch always. True, this phenomenon does occur, and NBTI is improved because of it. But can you guarantee that a transistor will always switch?"

Srikanth Krishnan said the benefits of annealing depend on an effect involving the transistor's history, which is difficult to capture for real-world devices. "Any model that claims to comprehend the annealing effect will have to be able to tell you the whole history of switching for this transistor over a long period of time. And we know that is not possible unless you know the exact path that the transistor took," he said.

Because the level of NBTI degradation is essentially path dependent, it is difficult to know how long any particular part of a circuit will be biased, he said.

The TI researchers agree with the Agere team that drive current degradation increases because of NBTI effects as channel lengths are scaled to 130 nm, 90 nm and beyond. Threshold voltage shifts due to NBTI are less directly dependent on device scaling, they said.

Capacitance problems
Working with 130-nm devices made with pure silicon dioxide gate insulators, the Texas Instruments team developed models that showed that the presence of interface traps creates important levels of degradation in the gate-to-drain capacitance, more commonly known as the Miller capacitance.

"Miller capacitance is a key parameter for both analog and digital circuits, and any change will affect circuit performance substantially," said Anand Krishnan. As oxides are thinned and NBTI becomes more important, companies will need to develop more comprehensive models that look at the mobility effects, in particular the impact on Miller capacitance, he said.

Also, companies need to test their parts with ac testing, as well as the typical dc tests. And better burn-in and test techniques are needed, they TI engineers said.

NBTI worsens at high temperatures, such as the 150 degrees C heat typical of burn-in or the 100 degrees C ambient temperatures a microprocessor reaches in normal operations. The heat creates stresses that shift the threshold voltage over time.

"So far, people have only modeled for the threshold voltage or for the drive current. They have neglected the impact on the gate-to-drain capacitance, and we know that the Miller capacitance changes greatly with NBTI stress, as much as 30 percent. That is pretty huge, and it needs to be comprehended in the Spice models," said Anand Krishnan.

The self-healing effect, however, may be a mitigating factor of 10 times or more at high frequencies, estimated Agere's Alam, providing perhaps a four times benefit for low-frequency devices.

If a company puts a reliability term of five years on its products, it may figure that NBTI effects could reduce the lifetime to four years or less, he said. "What my work is saying is that a product could be fine for 16 years, and more likely for 40 years. That can comfort the customers that these chips will be fine without changes in the process, that defects will be annealed and the chip can stay much longer in the field than expected."

Process engineers began seeing NBTI effects years ago, and began turning the various "knobs" that can reduce NBTI, including changing the boron concentration of dopants in the process, altering the gate bias slightly or even changing the gate voltage by 0.4 V or so.

Process engineers must guard against fluorine at the interface and should control the annealing temperature so the boron profile is well-controlled. Some companies add nitrogen close to the gate to improve NBTI, but must be careful to keep the nitrogen from diffusing into the oxide interface, which Mahapatra said "is a very tough thing to do for devices with very thin oxides."

"Technology [process] changes are expensive. Once engineers know about the problem, there are a lot of design tricks by which they can solve the problem. And modeling has been very effective," Alam said.

NBTI was the topic of an entire session at the recent International Electron Devices Meeting (IEDM). Alam and Mahapatra collaborated on one paper on NBTI there, and Alam presented a second paper himself. The Krishnans presented their work at IEDM as well, and said they will have further simulation results ready for presentation at the 2004 International Reliability Physics Symposium, planned for April in Dallas.






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