"Our most recent results show how to grow nanowires in precisely the places you want them on silicon wafers. Nanowires offer many advantages over nanotubes, such as the ability to dope them in different well-understood ways for different applications," said EE professor Rajendra Solanki at Oregon Health and Science University.

Next-generation nanoscale transistors using carbon nanotubes have grabbed kudos for their performance and high carrier mobility, but such problems as an inability to dope them or easily categorize them as metallic or semiconducting have spurred researchers to seek all-silicon alternatives.

Solanki claims to have found such an all-silicon process for adding nanowire transistor-channels to traditional silicon chips. He performed the work with fellow OHSU professors John Freeouf and John Carruthers, in cooperation with Portland State University scientists Shankar Rananavare, Jun Jiao and Rolf Koenenkamp.

The biggest problem with all forms of nanotechnology is that the nanoscale components are smaller than the tools used to create them. As a result, both nanotubes and nanowires have, until now, been fabricated as bulk freestanding components that are "shotgun" placed on a field of electrodes via evaporation deposition. Then direct visual inspection is required to determine which nanoscale components were deposited between which electrodes, as a precursor to testing.

Solanki's team's latest research show how nanowires can be grown in place between electrodes that have already been laid down with traditional micron-sized lithography. By shaping the electrodes as opposing arrows and applying a voltage potential between them, Solanki's team discovered that the nanowires would grow between the arrows' tips. Using a common process called vapor-liquid-solid deposition (in a quartz reactor), the researchers demonstrated that nanowires 5 to 20 nanometers wide can be grown between metal electrodes aimed at each other.

The dope on nanowires: Electron microscope image reveals 17-nm-wide silicon wires grown over a trench.

"So far we have just shown that you can precisely control where you grow nano-wires — both silicon nanowires, for devices, and nickel silicide conducting nanowires, for connections among devices," said Solanki. "Many devices will eventually be fabricated from these, not least of which [will be devices that use] a nanowire as the channel of a transistor by putting a gate electrode above it. The quantum effects that come into play at these small dimensions will enable many novel new devices to be made from nanowires."

The next step for Solanki's group is to more fully characterize the interface between the silicon nanowire and the metal electrode. So far the ohmic resistance of that interface is too high for fabricating devices, but Solanki is confident that his in-the-trenches engineering effort will reveal the conditions necessary to minimize the interface resistance.

"We also want to study how to control the passage of charge through the wires with surface impurities or coatings," said Solanki. Surface contamination, for instance, affects nanowires far more profoundly than micron-sized wires, simply because a nanowire may be less than 10 atoms thick, making even a single atom of contamination significant. Solanki's group hopes to leverage contamination by discovering impurities that enhance electron flow.

The group also plans to research ultrathin films by experimenting with alternating atomically thin layers of materials to create optical emitters and sensors for silicon nanowires that today must be offloaded to gallium arsenide chips.

Solanki's group received funding and other support from the Oregon locations of Intel Corp., Sharp Laboratories and FEI Corp. Oregon nanotechnology efforts include the National Center for Multiscale Materials and Devices (Corvallis). And the Senate sponsors of the 21st Century Nanotechnology Research and Development Act, which authorized $3.7 billion over four years beginning in 2005, included Oregon senator Ron Wyden.