These days, the excitement in EDA centers on electronic system-level tools and design-for-manufacturability. But usnsolved problems remain in plain-vanilla synthesis, placement and routing.

Three years ago, Jason Cong, professor of computer science at the University of California at Los Angeles, argued in a paper that contemporary IC placement algorithms leave so much wire length on the table that chip designs are essentially several technology generations behind where they should be. The "optimality gap" between actual and ideal placement results diverged by 1.46 to 2.38 times.

The paper sparked fresh academic research and inspired a placement contest that has been running for the past two years at the International Symposium on Physical Design (ISPD). One tangible outcome has been a set of real-world benchmark circuits. In this year's contest, UCLA's mPL6 placer produced the best wire length, but the Technical University of Munich's Kraftwerk placer, with faster run-times, took first place.

As a result of the recent research, the optimality gap between actual and ideal placement results is down to 20 or 30 percent, Cong said. But Igor Markov, professor of electrical engineering and computer science at the University of Michigan, suggests there's more room for improvement. Markov says that his university's Rooster placer resulted in a 26 percent post-route net length improvement over Cadence Design Systems' AmoebaPlace algorithm, albeit with slower run-times. Rooster, by the way, did not do particularly well in the ISPD 2006 placement contest.

Cong's latest work suggests that FPGA synthesis algorithms may produce circuits that are 70 to 500 times larger than optimal solutions in synthetic benchmarks (see Feb. 20, page 1). That doesn't mean real-world circuits are that far off, but it suggests more work is needed. Cong hopes to spark new interest in logic synthesis research. Next month's International Workshop on Logic Synthesis is sponsoring a contest on logic synthesis.

It's good to see these less-glamorous, but still critical, areas of IC design automation get their due.

Richard Goering (rgoering@cmp.com) is group editorial director for design automation at EE Times