San Jose, Calif. -- A handful of high-speed interconnects are about to hit the market, driving changes in how designers will handle fast signals.

The Scalable System Packet Interface (SPI-S), scheduled for release today by the Optical Internetworking Forum, aims to carry data at 6 Gbits/second and up between chips or boards in a communications system.

As early as this month, the PCI Special Interest Group could finish the spec for PCI Express 2.0, which uses a native 5-GHz signaling rate. And the RapidIO Trade Association has been touring the United States and Asia to discuss its 2.0 spec for interconnects, running at up to 6.25 Gbits/s.

While the technologies target a variety of sometimes-overlapping tasks in communication and computer systems, all will become options in the board designer's tool chest. At the same time, the move to the higher data rates will demand new techniques in interconnect design, especially signal integrity.

"Five and 6.25 Gbits/s are not the urgent need of the industry today, but the technology is available and definition by a standards body is important before a de facto choice just happens," said Tom Cox, executive director of the RapidIO group.

SPI-S arrives at a time when comms giant Cisco Systems Inc. is well down the road to making an internally developed protocol called Interlaken a staple in the many ASICs it designs for its systems. Known within Cisco as "Spaui"--because it's a mix of the existing SPI 4.2 interconnect and Xaui, a 10-Gbit Ethernet link--Interlaken will appear on at least a dozen of the 15 or so ASICs in the works at Cisco's storage-networking group alone.

Cisco co-developed the interface with Cortina Systems Inc. (Sunnyvale, Calif.) and announced last April that Cortina would make it available as a royalty-free download. Like SPI-S, Interlaken rides on top of the Optical Internetworking Forum's Common Electrical Interface (CEI) as a physical transport. The Spaui link is serving Cisco well, according to Tom Edsall, a senior vice president of Cisco's Datacenter Business Unit and chief architect of its MDS 9000 storage switch.

What is SPI-S?
SPI-S is an attempt by the OIF to deliver a protocol that has gone through its formal standards process. Like Interlaken, it is independent of any physical transport but is designed to ride on the short- and long-reach versions of CEI, currently defined at 6 and 11 Gbits/s.

Both protocols act as upgrades to the existing SPI 4.2 link. SPI 4.2 defined both protocol and physical layers and was thus fixed as sixteen 600- to 900-Mbit/s channels. By contrast, SPI-S or Interlaken could ride on any future higher-speed physical interconnect.

The OIF, an ad hoc consortium of chip and systems companies, started work on a 25-Gbit/s electrical layer earlier this year that may not be ready for 18 to 36 months.

"SPI-S will scale to any width or electrical-signaling rate, so that in the future, we should not have to reinvent the protocol for every new generation," said Dave Stauffer, an IBM Corp. ASIC engineer and the chairman of the OIF's physical- and link-layer working group, which defined SPI-S.

Fred Olsson, a product manager for Cortina, said that Interlaken was developed about 18 months ago as a quick-to-market attempt to boost board signaling rates while the SPI-S work was still in progress. "There was a fairly urgent need for something, and people were working on proprietary technologies," Olsson said. "But we wanted something open."

Cortina has no plans to upgrade or charge licensing fees for Interlaken. The company wants the protocol to become widely adopted, because it will use Interlaken in networking chips slated for release in 2007, he added.

Interlaken and SPI-S have a number of technical differences that make Interlaken the preferred choice for Cisco, said Ramesh Sivakolundu, director of ASIC engineering in Cisco's data center business unit. While SPI-S uses a popular 64/66 encoding method, Interlaken uses 64/67, which "provides better running disparity in case we are using a serdes connection with dc coupling," he wrote during an e-mail exchange.

Interlaken has 24-bit cyclic redundancy checking, compared with 12-bit CRC for SPI-S. In addition, flow control is simpler in Interlaken, which implements other mechanisms--such as meta- frames–that are not found in SPI-S, Sivakolundu wrote.

Both SPI-S and Interlaken are aimed at linking traffic-framing and network-processing chips on a single card or over a backplane at speeds faster than SPI 4.2. The streaming semantics of the OIF interconnects are geared for fast and reliable packet handling in a comms system.

By contrast, PCI Express and RapidIO both implement a more CPU-centric model based on direct-memory access (DMA), said Brian Holden, co-chair of the OIF's marketing group and a principal engineer at PMC-Sierra Inc. In the event of a system failure, the SPI links tend to automatically re-establish a connection. By contrast, interconnects based on DMA tend to require a manual reboot after a system failure, Holden said.

Express and RapidIO
The 5-GHz PCI Express 2.0 is indeed mainly geared for computers. It is expected to be used first for bandwidth-hungry graphics and later for server and storage applications. However, because Express 1.0 is becoming so popular based on high-volume use in PCs, the new version could see a big uptake in embedded and communications systems as a low-cost option in the future. The spec is now in final review and could be completed before the end of the year.

A companion electromechanical spec defining eye diagrams and compatibility is still in a version 0.7 draft stage but should be done by June. Compliance and interoperability tests for PCI Express 2.0 are expected to roll out by the end of 2007, with products ramping in 2008.

Serial RapidIO, which will support 5- and 6.25-Gbit/s transmissions, has yet to come to a final ballot in the trade group. The association has been presenting details of the spec to engineers in a road show across the United States, Japan, China and India.

RapidIO 2.0 will ride on top of the 3.125-Gbit/s Xaui electrical interface or the same OIF CEI physical layer used by SPI-S. It will support one, two, four, eight or 16 channels. New features in version 2.0 include a streaming-packet format, virtual channels, a traffic-management specification and an endpoint flow control arbitration spec.

SPI-S will primarily be used to link framer and packet-processing chips. By contrast, said Cox of the RapidIO Trade Association, RapidIO will be used for a broader variety of chip-to-chip, backplane and fabric applications, especially those requiring DMA semantics.

Inside the eye
All the new interconnects are likely to raise new signal integrity issues for board designers. "At 3 Gbits/s across 30 inches or so, you still have a reasonable eye at the transceiver," said Todd Westerhoff, a vice president for software at SiSoft (Maynard, Mass.). "But when you get to 6 Gbits, there is nothing to measure--the game changes."

"Traditional oscilloscopes and test probes are becoming less and less useful," said Howard Johnson, a consultant with Signal Consulting Inc. (Twisp, Wash.). "We should change the way we test signals for things like integrity."

At 6 Gbits and higher, transceivers routinely use signal-conditioning and filtering techniques to help capture signals across a board. But each chip maker has its own approach to applying such pre-emphasis and equalization techniques. Engineers need a standard way to create a closed loop between the high-speed transmitters and receivers from various vendors so the chips work out their differences, Westerhoff said.

"All the 6-Gbit systems will need some facility to let these two chips talk over control software to get optimized," he said. SiSoft is one of several companies working on products to address the issue.

Sivakolundu of Cisco said the company has faced many challenges with designs at 6 Gbits/s and faster. These have included conforming to CRC24 and CRC32 specs, designing a good scrambler and descrambler scheme, and synchronizing the receiver and transmitter.

Other issues included mapping internal virtual and external physical lanes. Cisco designed a universal solution that can use any lanes up to a set maximum. Handling the link-level and per-channel flow control in one system has also been a problem, Sivakolundu added.

For many engineers, the 6-Gbit issues are still on the horizon. Most observers said that the vast majority of high-speed interconnect design today is still being done at 1 to 3 Gbits/s. "A few companies have 5- to 6-Gbit stuff in the labs, but it's a small sample," said Westerhoff.

Nevertheless, Johnson of Signal Consulting said the industry should make bolder moves toward fast signaling. He noted that chip- and board-level interconnects tend to double data rates every several years, while Ethernet takes tenfold leaps in that same time frame.

"I wish we had the balls to do that in chip-to-chip interconnects. Many small steps are not that helpful," Johnson said. "You wind up with designs that need to support a wide range of speeds and voltage levels. I have worked with some people who have eight voltage regulators on their board."

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