1. Electronic design — surviving the inflection point.

Smith has been talking about an "inflection point" in EDA, driven by the move to electronic system level (ESL) design, for some time. This inflection point is compounded by the requirements of design for manufacturability (DFM) in the IC physical design flow, Smith said. It's similar to the late 1980's, Smith said, when there was a move to RTL design and synthesis, and Cadence Design Systems came out with the next generation of IC CAD tools.

2. ESL — moving from a semiconductor design-driven market to an embedded FPGA/microprocessor design driven market.

There are three groups of designers using ESL tools, Smith said — system-on-chip (SoC) designers, system designers, and "strictly embedded guys." The system designers, he said, are starting to use FPGAs in conjunction with microcontrollers. "It looks like the semiconductor group may account for only 22 percent of revenues," Smith said. "If the market really takes off, the main players are going to be the embedded designers. Otherwise there's going to be a 50-50 split between embedded and system designers."

3. DFM/DFY — is the real DFM emerging?

Smith said that Clear Shape Technologies, which introduced its InShape and OutPerform offerings in November, is offering the first real DFM tool. "It's the first one targeted for the designer," Smith said. "All the rest have been post-GDSII tools." Design for yield (DFY), Smith noted, is a post-GDSII exercise aimed at changes that might help improve yields.

4. Second generation SoC — it's the software, stupid

In a presentation at the Design Automation Conference in July, Smith emphasized that the biggest problem with SoC design is embedded software development, telling the audience that "it's the software, stupid." Now, said Smith, the message has come back to the semiconductor and ASSP companies that reference designs must include software. "What we've seen is that the ASSP and ASIC guys are hiring more software engineers than hardware engineers," he said. "They're waking up to the problem."

5. IP usage — will we ever reach the 80-90 percent die area goal?

"When we first started looking at IP [intellectual property] in the late 1990s, the idea was that IP was going to take up 80 to 90 percent of the die," Smith said. "We have been sort of stuck between 55 and 70 percent of the die area for the last four years." What might break that bottleneck, he said, is that fabless semiconductor companies are starting to get into the IP market. "That makes a lot of sense, and could be the answer to getting a lot more IP on the die," Smith said.