San Jose, Calif. -- Toshiba Corp. is rolling out four enabling technologies in a multipronged drive into the booming embedded NAND flash-memory market.

The technologies--aimed at boosting the error correction code (ECC) functions and other design problems with NAND flash--include logical block addressing (LBA) NAND; gigabyte (GB) NAND; GB multichip package (MCP); and package-on-package (PoP). LBA-NAND and GB NAND are single-component solutions while GB MCP and PoP are chip packages.

The solutions use Toshiba's new 56-nanometer, multilevel cell (MLC) NAND flash-memory devices. Toshiba (Tokyo) expects the market for embedded NAND to grow from $6.3 billion in 2006 to $12.9 billion in 2010. Toshiba is the world's second-largest NAND flash supplier, after South Korea's Samsung Electronics Co. Ltd. (Seoul).

Designs incorporating NAND flash are exploding in consumer electronics. But NAND also poses inherent challenges for designers, such as a shift from 4- to 6-bit ECC and complex software drivers.

Another headache is the transition from single-level cell (SLC) NAND architectures to MLC devices.

"MLC requires better error correction," said Doug Wong, a member of the technical staff at Toshiba's U.S. chip unit, Toshiba America Electronic Components Inc. (Irvine, Calif.).

To help designers on that front, Toshiba has rolled out 56-nm devices based on two technologies: LBA-NAND and GB NAND. Today's NAND flash uses the physical-address access method that defines each physical page of a memory, from the chip to the block, to the page and down to the cell. Engineers must develop host side and driver specifications that can recognize and accommodate this physical addressing or use third-party controllers.

LBA-NAND, Toshiba said, solves many of those issues. The logical-address access method of LBA assigns each cell a unique address that is not geometry-dependent. The first cell is simply 0, and numbering will continue to cover every cell. Assigning a new address to each cell allows increases in memory capacity to be accommodated more easily, Toshiba said.

That approach also allows block management, ECC and wear-leveling--all of which are controlled by the host side--to be handled on the memory side by the LBA-NAND controller.

Toshiba's first LBA-NAND parts, built in a 56-nm process, are available in 2-, 4- and 8-Gbyte capacities. The products also boast 8-bit ECC, 10,000 write/erase cycles, 5-Mbyte/second write performance and greater than 10-Mbyte/s read performance.

The 2- and 4-Gbyte devices are slated for production in the second quarter; Toshiba did not disclose the schedule for the 8-Gbyte product. The parts come in a 48-pin TSOP package and are drop-in replacements for comparable SLC NAND devices.

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