COLORADO SPRINGS, Colo. — Tundra Semiconductor Corp.'s Silicon Logic Engineering Division is offering intellectual-property cores for the new scalable Interlaken standard. The licensable IP can be used in ASICs and FPGAs. The latter market is particularly relevant, since Altera Corp. announced the release of its Stratix II GX FPGAs, which target the Interlaken interface. Cortina Systems Inc. and Cisco Systems Inc. developed the standard.
While the serial link is touted currently for its 40-Gbit/second capabilities, the IP core from SLE can scale from 10 Gbits/s to beyond 60 Gbits/s. SLE plans to develop future versions scaling to 120 Gbits/s. The serializer/deserializer blocks scale from 3.125 to 6.375 Gbits/s per lane, and SLE plans cores with anywhere from 1 to 24 serdes lanes per design. The core requires independent serdes interfaces, though many semiconductor vendors already offer on-chip serdes blocks.
Cisco and Cortina developed Interlaken to combine elements of the extended attachment unit- and serial peripheral 4.2 interfaces, adopting per-channel flow control and channelization from SPI 4.2, and high-speed serdes designs from Xaui.
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