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Experts spar over limits of IC scaling
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EE Times


SAN FRANCISCO — During a panel session at this week's IEEE International Solid-State Circuits Conference (ISSCC) here, experts disagreed over the future limits of IC scaling. Some believe that bulk silicon still has legs. Others thought scaling was over. And some were not sure.

''When will scaling fail? It already has,'' said Bob Brodersen, the John Whinnery chair professor and co-scientific director of the Berkeley Wireless Research Center at the University of California at Berkeley.

Broadersen indicated that chip scaling became less important — and fell apart — during the shift towards the multi-core processor era, when power consumption and leakage was more of a concern than overall clock frequency.

Now, as the PC industry moves towards eight-core processors and beyond, the key is software, not hardware. ''Parallelism is the key to the future of performance,'' he said. ''Can the software industry meet this challenge?''

He even took a swipe at Intel Corp.'s 80-core R&D chip, which was re-introduced this week. ''How do you program that thing?'' he asked.

Not surprisingly, Intel insisted that scaling is not over. Mark Bohr, an Intel senior fellow and director of process architecture and integration at the microprocessor giant, said that future devices could theoretically scale down to 1.5-nm, with 0.04-ps switching speeds and 0.017 electron volts in terms of power consumption.

Bohr's forecast was based on a paper by V. Zhirnov in the November 2003 issue of "Proceedings of IEEE," where the minimum quantum well dimensions were estimated to be 1.5-nm.

Besides scaling, there will be other major barriers going down the technology curve. ''Power density is the limiting factor,'' Bohr said. ''There will be less emphasis on frequency and a new emphasis on power efficiency.''

In addition, voltage barriers, velocity limitations and variability are becoming a concern going forward, said Hans Stork, senior vice president and chief technology officer at Texas Instruments Inc. ''The physics are working against us,'' Stork said.

So, one thing is for certain: the industry will need a new breakthrough in the post-CMOS era if or when bulk silicon runs out of gas, declared James Meindl, professor of microelectronics at the Georgia Institute of Technology, in the panel, entitled ''Ultimate Limits of Integrated Electronics.''

''What we really need is a huge breakthrough," Meindl said. ''We need new technology.''

As previously reported, no consensus or cost-effective device technology has emerged for the dreaded post-CMOS era, less than a decade away, researchers warned. That era — when the bulk silicon in today's chip-making fabs no longer scales — could hit by 2015 or sooner. By that time, fabs would need a replacement technology, such as carbon nanotubes, nanowires, molecular electronics, quantum computing, three-dimensional transistor designs and spintronics.






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