Fabless silicon intellectual-property vendor Ceva Inc. (San Jose, Calif.) has introduced the Ceva-TeakLite-III family of digital signal-processing cores, targeting 2.5G and third-generation cellular basebands, high-definition audio, voice-over-Internet Protocol and portable audio players. The first three family members, the TL3210, TL3211 and TL3214, are assembly-code-compatible with previous-generation TeakLite cores but incorporate many enhancements.

Of particular interest to DSP developers is the addition of 32-bit and dual 16 x 16-bit multipliers. (The TeakLite I and II have only a single 16-bit multiplier.) The 32-bit multipliers offer the increased precision needed for high-fidelity audio applications, while the dual 16 x 16-bit multipliers boost performance for a wide range of DSP applications.

The TeakLite-III also gets a speed boost from new audio-oriented instructions and instructions for accelerating fast Fourier transform, Viterbi and Huffman algorithms. Initial performance estimates by Ceva show TeakLite-III cores to be 4x faster than previous TeakLite cores on basic operations and twice as fast on most popular audio codecs. The cores will operate at 350 MHz in a 90-nanometer process and up to 425 MHz in a 65-nm process. The company largely enabled the increase in clock speed by deepening the pipeline to 10 stages, up from four stages in previous TeakLite cores.

Migration to 32 bits
Other changes include migration to a 32-bit architecture (TeakLite I and II were 16-bit architectures) and new RISC features. The RISC features include a 32-bit general-purpose register bank, a 32-bit linear address space that extends the addressable memory to 4 Gbytes and a cached-memory subsystem that frees the developer from managing memory.

Branch prediction and conditional instructions improve the performance of decision-making code.

The TeakLite-III nominally uses 32-bit instructions, but it also supports a comprehensive 16-bit instruction set. An entire application can be written using only the 16-bit instructions, or programmers can mix 16- and 32-bit instructions. That flexibility allows developers to make trade-offs between code size and performance.

Other instruction sets, such as the instructions for the ARM Thumb2 core, offer similar capabilities.

TeakLite III continues the trend in DSP cores of incorporating more control functionality. It will likely compete against other dual-MAC DSPs, such as Texas Instruments' C55x+, which runs at 400 to 500 MHz under worst-case conditions. It will also compete with 32-bit RISC processors that incorporate DSP functionality, such as the ARM11 and MIPS24KEc cores.

Ceva reports that two top-tier semiconductor companies have licensed TeakLite III cores: a U.S.-based vendor developing a multimode baseband chip and an Asian vendor developing chips for high-definition audio applications.

The Ceva-TL3210 and TL3214 are available for licensing today. The TL3211 is slated for licensing in early 2008.

Kenton Williston is the site editor of DSP DesignLine (www.dspdesignline.com).