Designers developing mobile handsets must accommodate ever-more-demanding user requirements, including increased functionality, lighter weight, lower cost and longer battery life. Additionally, state-of-the-art handsets continue to shift to higher RF frequencies, as a result of overcrowding of existing unlicensed bands as well as the need to deliver the higher data rates demanded by applications such as video streaming.

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Advanced handsets can operate on a number of frequency bands. The RF switching needed to provide the integration and connectivity for these multiple bands to the antenna is testing the limits of conventional technology. The antenna switch module (ASM) is usually the tallest device in the radio section of the handset, and it draws a fair amount of current. Technologies that reduce the form factor and power consumption of the ASM are therefore of great interest.

An increasingly popular alternative for front-end switching is RF CMOS. Leading-edge CMOS technology has enabled the fabrication of ICs with mind-boggling device densities and performance, providing RF designers with the manufacturing advantages of CMOS (integration, power, cost, manufacturability and scalability) and the improved RF performance that process scaling can bring. Though the silicon substrate in a bulk device is excellent for the fabrication of active devices, it is a compromise material that provides neither perfect isolation nor conduction. Silicon can limit RF performance by capacitive coupling of the RF devices to the resistive substrate. That leads to dissipation of RF energy, poor-quality-factor passives, crosstalk, and injection of thermal noise back into the circuit.

An alternative CMOS technology, silicon-on-insulator (SOI), consists of a layered silicon-insulator-silicon substrate. On SOI-based devices, the silicon junction sits on the insulating layer (usually silicon oxide) and enables complete dielectric isolation of devices. Additionally, bonded SOI substrates may be used to combine high-resistivity substrates with standard IC processing. The insulator used in an SOI device is typically silicon dioxide or, less commonly, sapphire. Traditionally, sapphire was used for radiation-sensitive applications (aerospace and military), while silicon oxide was preferred for improved performance and diminished short-channel effects in microelectronic devices.

SOI devices generally have lower parasitic capacitance than bulk silicon devices and can reduce power consumption at matched performance. A further benefit of SOI is latchup resistance due to complete isolation of the n- and p- well structures. SOI substrates are compatible with almost all conventional wafer-fabrication processes and can be implemented without significant retooling of an existing factory. Furthermore, SOI substrates are readily available at 300-mm diameters.

Silicon-on-sapphire (SOS) has for years been recognized as a technically superior semiconductor vehicle and the ultimate form of SOI, offering silicon on a perfect isolator with no parasitic capacitance at high-frequency operation. But price, yield, availability and process issues have limited SOS to specialized military and aerospace projects.

NMOS transistor in the CMOS logic area of the PE42612.

In the past few years, SOS has been significantly improved, as demonstrated by Peregrine Semiconductor's process achievements, which addressed yield problems and enabled more cost-effective commercialization of the technology. Peregrine's technology enables the type of RF solutions required for multiband ASMs. In April 2004, Peregrine Semiconductor announced a broad licensing agreement with Oki Electric Industry Co. Ltd. that transferred Peregrine's 0.5-µm UTSi SOS to Oki's Hachioji, Japan, plant. That move opened the way to multiple sourcing and expanded design libraries.

The cornerstone of Peregrine's SOS process is heteroepitaxial growth of single-crystal silicon on sapphire (Al₂O₃). Lattice mismatch of the silicon with the sapphire substrate results in lattice defects, primarily so-called twin defects. Implanting the substrate with silicon to create an amorphous silicon layer near the silicon-sapphire interface is followed by solid-phase epitaxial (SPE) regrowth from the top silicon surface toward the interface. That enables the amorphous silicon layer near the interface to be regrown with minimal lattice defects.

The silicon layer is then thinned by oxidation to consume remaining defects near the surface, eliminating twin defects and bandgap states and resulting in a pure single-crystal silicon layer for CMOS devise fabrication. It is formed on a single-crystal silicon film that was previously grown on the sapphire substrate. By forming a recessed local-oxidation-of-silicon isolation structure to separate active areas, well regions normally required for device isolation in bulk silicon substrates are not necessary. The combined footprint of the source, drain and channel is accordingly very small, minimizing junction capacitance.

Die photograph of Peregrine Semiconductor's PE42612 SP4T RF switch. The image was taken though the backside of the transparent sapphire substrate.

The early drawbacks of SOS technology included lattice mismatch, stress-induced delamination and poor interface quality. Die size was limited by substrate nanotopography, and lattice defect density added to the obstacles. These problems have been largely addressed and will continue to diminish.

Today's substrates are still limited to 150-mm diameters, and while surface roughness is less than 5 angstroms root mean square (compared with 1.5 Å rms for SOI substrates), these issues may still limit the level of integration possible with this technology for some time. Further, large-diameter sapphire wafers add to the overall cost of the devices.

On the positive side, SOS provides full dielectric isolation with no substrate capacitance, and no back gate is required. The higher thermal conductivity of sapphire eliminates self-heating effects inherent in the thermally insulated body of SOI devices. This improves backside cooling for flip-chip-mounted devices. Given that SOS technology can reduce complexity of SiGe-based processes by up to 50 percent, these advantages may override the drawbacks of SOS and provide a compelling enough advantage to control costs and entice designers.

The PE42612 UltraCMOS SP4T switch is an antenna switch module that has been commercialized using SOS technology. The insulating sapphire substrate eliminates the parasitic drain capacitance, making devices like this one well-suited for use in triple- and quad-band GSM systems. Additionally, the integrated decoder/drivers made possible by the CMOS logic of the SOS technology eliminate the need for the offline decoders, blocking capacitors and diplexers normally required with other technologies.

The device is manufactured using Peregrine's single-poly, three-metal FA process and is flip-chip mounted. As of early 2006, Peregrine had already shipped more than a million devices for use in GPRS handsets. Increasingly complex and integrated switches, such as the SP7T HaRP SOS switch, are being designed and manufactured. n

John Boyd (johnb@ semiconductor.com) is product technology manager for process technology at Semiconductor Insights (Kanata, Ontario). He holds more than 60 U.S. patents.