With the migration to 45-nm cores, optimized I/O planning and placement will become even more critical. These challenges beg the question: Who should take charge of a chip's I/O plan, along with the considerations for the package and the rest of the system?

Unlike the internal workings of the IP core, I/Os will not shrink to 45-nm technology, for several reasons. Although new 45-nm cores have smaller geometries and can therefore operate at lower voltages, I/Os must deal with other devices in the system that are not 45-nm designs but must still handle higher voltages. For example, if other chips are switching at 1.8 volts, then the I/Os on the new 45-nm design must also switch at 1.8 V, even though the core may be operating at 1.0 or 1.2 V.

I/Os must be robust so as not to be compromised by higher switching voltages. Most I/Os in use today are developed by third-party vendors, not necessarily by the company designing the 45-nm core. These IP providers typically do not live on the cutting edge of process nodes and thus lag in releasing new libraries.

In addition, it takes significant time and effort to design and characterize I/Os. Compounding the challenge are companies that do not want to be the first ones to use next-generation I/Os, because those elements have not been fully battle tested.

Finally, serializer/deserializer (serdes) transceivers--chips that convert parallel data to serial data and vice-versa--are self-contained macros that can include analog circuitry. Serdes are huge compared with other I/Os, and their size has an impact on I/O planning and placement. Other circuits and I/Os must be efficiently placed around serdes blocks.

System-level planning provides view of interconnects. Early I/O and package plan allows analysis of chips I/O buffers to PCB contacts

High-speed serdes networks require specific placement with respect to how devices will fit within the rest of the system. As a result, it is critical to consider system requirements when placing serdes blocks. This system- or pc-board-driven flow is a critical element for successful implementation of high-speed nets.

To combat the challenges, differential pairs--pairs of conductors with special characteristics used for differential signaling circuits--are increasingly being used. Differential circuits require specific I/O placement and planning to assure proper routing on package and board. The unmistakable conclusion is that methodologies to support system-level I/O planning are a must for 45-nm implementation.

Migrating to 45 nm
Three types of designs are being migrated to 45-nm design: design implemented for cost reduction, completely new designs, and next-generation designs to meet designers' specific challenges.

Reducing the core and die sizes will help reduce cost but can result in a pad-limited design. The I/O can restrict the amount of die reduction that can take place. Thus, to take full advantage of the new technology, the I/O plan needs to be redesigned for better efficiency.

In most cases of technology migration for cost reduction, the package or board will not be changed. That means the new I/O plan must reuse the existing package ball-out as well as the existing core requirements. The only way to reuse the existing package or board successfully is to have a methodology that can honor constraints from both sides. Successful implementation makes the most efficient use of the die area while honoring reuse requirements.

Unified data model facilitates optimization process. Design elements are part of synthesis flow via OpenAccess database

In a new design, the goal is not to save money but to add functionality. Here, the original core is reduced in size, and circuitry is added. With more circuitry comes more I/O. Further, there may still be a reuse element on the package or board side. The challenge is to implement the new circuitry while honoring any reuse constraints. Those constraints may be a predefined serdes placement, differential-pair ball-out or existing analog circuitry. The methodology must build a new I/O plan around the existing circuitry and constraints.