With the launch of Intel's P35 chip sets, the growing list of validated devices and AMD's planned support, DDR3 SDRAMs have become a reality.

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Intel has validated DDR3 SDRAMs from manufacturers including Elpida, Hynix, Micron, Nanya, Qimonda and Samsung. The compliant devices have densities of 512 Mbits and 1 Gbit, with performance ratings of 800 MHz and 1,066 MHz. Most are manufactured in 90- or 80-nm process nodes. Given the pace of DRAM manufacturers' migration to devices that are 70 nm and smaller--which will make 1-Gbit DDR3 SDRAMs more cost-effective--some industry experts predict the 512-Mbit DDR3 market will become insignificant compared with that for 1 Gbit and higher.

Semiconductor Insights performed comparative analyses on two of the leading 1-Gbit DDR3 SDRAMs, from Samsung and Micron. The devices are manufactured in comparable process nodes--Samsung's in 80-nm lithography and Micron's using 78-nm lithography.

Samsung 1-Gbit, 80-nm DDR3
The Samsung sample has a die size of 127 mm, and the DRAM cell size is 0.053 µm. Bonding pads are located in the center of the chip in two rows. The internal data bus and the related pipeline circuitry supporting the DDR3 8-bit prefetch architecture appear to be placed in the center of the chip vertically. Compared with the Micron 1-Gbit DDR3 SDRAM, the use of two rows of bonding pads appears to allow more signal routing channels between the upper 512-Mbit half and the lower 512-Mbit half.

A close-up of the Samsung DDR3 shows the internal data bus and related pipeline circuitry centered vertically with the bonding pads in the center of the chip in two rows. Source: Semiconductor Insights

Two rows of column decoders appear to be placed in the upper and the lower half of the chip. This reduces the length of column select lines compared with the Micron architecture. Samsung's architecture appears to be designed to achieve high performance by having shorter column select lines and shorter local data bus lines.

Samsung's DRAM cell is an 8F² cell with a metal-insulator-metal (MIM) capacitor. The DDR3 device uses a spherical recess-access transistor with a gate length of 47 nm. The wordline width and pitch are 47 µm and 165 nm, respectively. The bitline width and pitch are 40 nm and 160 nm.

Micron DDR3
The Micron 1-Gbit DDR3 sample's die size is 102 mm², and it has 38 percent cell efficiency. Micron's 6F² cell, with an area of 0.0365 µm², is the smallest DRAM cell that Semiconductor Insights has analyzed.

It appears that use of copper interconnect for metal 2 and metal 3, combined with smaller cell size, helped Micron designers achieve desired performance with 1-Gbit DDR3 design. Despite there being a long distance for signals to travel in the larger die, relatively low resistivity and a low-profile copper interconnect helped reduce signal resistor-capacitor (RC) delay as well as power consumption.

A close-up of the Micron DDR3 shows one row of bonding pads horizontally in the center of the die with column decoders, internal data bus, and pipeline control circuitry arranged in the center of the die next to memory arrays. Source: Semiconductor Insights

Compared with Micron's 110-nm, 512-Mbit DDR2 design, the main wordline lengths appear to have been halved in the 1-Gbit DDR3 design. Relatively short main wordlines and the use of copper data lines are merits for DDR3 operation, especially for lower-latency and higher-speed operations.

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Micron uses a 6F² cell design with a MIM capacitor and a recessed-channel access transistor. The wordline width and pitch are 63 nm and 156 nm, respectively. The bitline width is 80 nm--the same as that of the Samsung 80-nm DDR3. The bitline pitch is 156 nm, slightly smaller than Samsung's 160 nm.

The 6F² cell implementation reduces the Micron die's chip size by 24 percent compared with Samsung's. Each DDR3 SDRAM design shows distinguishing features: Micron's design uses a single row of bonding pads, while Samsung's uses two rows of bonding pads. Data bus manipulation and pipeline handling appear to take place i the periphery area of Micron's design. Samsung, however, has these operations performed by distributing them across the memory array area.

Comparison of DDR2 and DDR3
Currently, DDR3 SDRAMs cost two to three times as much as DDR2 SDRAMs. Semiconductor Insights' analyses of DDR2 and DDR3 designs from multiple manufacturers show that the typical DDR3 chip size premium over DDR2 is between 22 and 23 percent. That translates to about 20 percent fewer gross dice per given wafer. For example, a 300-mm wafer generating 90-nm devices can yield about 950 DDR2 gross dice. DDR3 design, on the other hand, would result in only 770 gross dice with the same 90-nm technology.

The cell efficiency for DDR3 designs ranges from 33 to 45 percent, whereas the cell efficiency for DDR2 designs of the same technology is much higher, measuring between 41 to 54 percent. The wide internal data bus and the related circuitry, including data read/write amplifier and multiplexing circuits to support 8-bit prefetch architecture, consume precious silicon area. Extra pipeline stages to support DDR3's high-speed I/O, improved on-die termination circuitry and other features contribute to the die size overhead. Given DDR3's relatively low cell efficiency, higher-density DDR3 designs (1 Gbit and higher) make the most sense from a cost perspective.

Memory vendors began sampling DDR3 SDRAMs this summer, but high-volume sales are not expected until mid-2009, when DDR3 is predicted to reach price parity with DDR2. The DDR3 SDRAMs announced so far can perform up to 1,066 MHz. That is comparable to the performance of the high-end DDR2 SDRAM devices currently available. But the market expects more than DDR2 performance to justify a switch to DDR3.

Some overclocked DDR2 modules actually have higher performance than available DDR3 modules. To demonstrate clear advantages for DDR3, devices with 1,033-MHz or even 1,600-MHz performance would be required. Components for the highest-speed, 1,600-MHz versions will become available when manufacturers transition to 70- and 6-nm DRAM geometries, which is expected to happen sometime between 2008 and 2009. With that process migration, 2-Gbit and higher-density DDR3 SDRAMs will become more cost-effective for adoption, first in the server market and later among general PC users.

Young Choi (youngc@semiconductor.com) is product technology manager for memory at Semiconductor Insights (Ottawa).

 Comparison of 1Gbit DDR3 samples shows that Samsung has achieved a higher cell efficiency.
Source: Semiconductor Insights

 A relative chip size overhead comparison of DDR3 over DDR2 shows the relatively low cell efficiency of DDR3 designs.
Source: Semiconductor Insights