For more than two decades, chip makers have developed digital IC products with on-chip ESD protection circuitry that supports the 2,000-V level for the Human Body Model (HBM) and the 200-V level for the Machine Model (MM).

The Industry Council on ESD Target Levels is now pushing the industry to lower the HBM level to 1,000 V and the MM target to 30 V.

The council, which was formed last year, consists of 16 major companies: Analog Devices, Advanced Micro Devices, Freescale, Fujitsu, IBM, Infineon, Intel, LSI, Matsushita, NXP, Oki, Renesas, Samsung, Sarnoff, Texas Instruments and TSMC.

"Today's enhanced static control methods required by OEMs do not justify these higher HBM/MM levels as data shows in this document," according to two members of the group, Charvaka Duvvury and Harald Gossner.

Gossner is a senior principal for ESD design at Infineon Technologies AG (Munich, Germany) and co-chairman of the Industry Council on ESD Target Levels. Duvvury is a fellow in Texas Instruments Inc.'s (Dallas) Silicon Technology Group and co-chair of the group.

"ESD over-design to these levels in today's latest silicon technologies is increasingly constraining silicon area as well as performance, and is leading to more frequent delays in the product innovation cycle. Based on improved static control technology, field failure rate, case study and ESD design data, collected from IC suppliers and contract manufacturers, we propose a reduction to more realistic yet safe HBM/MM ESD target levels," according to the two technologists.

The white paper, entitled "A Case for Lowering Component Level HBM/MM ESD Specifications and Requirements," is now available for public access here.

''This document was written with the intent to provide information for quality organizations in both semiconductor companies and their customers to assess and make decisions on safe ESD level requirements,'' according to the group members.

''We show through this document why realistic lowering of the ESD target levels for component level ESD is not only essential but is also urgent,'' they added. ''All component level ESD testing specified within this document adheres to the methods defined in the appropriate JEDEC and ANSI/ESDA specifications.''

Not all are in agreement. Some members in the group did an about-face about their view on the matter, especially Sarnoff Europe, part of Sarnoff Corp. (Princeton, N.J.).

NEC Electronics Inc., for one, recently developed a new electrostatic discharge (ESD) technology for the 45-nm node. "Because of the shrinking geometries of devices at the 65-nm node and smaller, voltage and current tolerances at the circuit level have become ever more stringent. But smaller geometries require the same level of ESD protection as larger ones," according to NEC.

"It's up to the customers to decide" their respective ESD requirements — as opposed to an industry group, according to one expert in the field.