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IMEC claims variability-aware design flow at 45-nm
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EE Times Europe


MUNICH, Germany — Research institute IMEC vzw (Leuven, Belgium) is has demonstrated a variability-aware IC design flow as a result of work with Qualcomm and Samsung as its first two top-tier industrial partners in a Technology-Aware Design program.

The flow has been proven with reference to an ARM processor core on a TSMC manufacturing process and adds to standard IC development steps with the ability to analyze process variability of sub-45-nm technologies. This enables designers to optimize their system design for timing, energy and yield versus expected application load. The flow can hook into commercial design for manufacturing (DFM) tools and has been validated on industrial process technology data and IP cores, IMEC said.

The VAM flow can move information on process variability of sub-45nm technology from the transistor up to the system level and enables IP block and system designers to make predictive assessment of architecture design options before manufacturing.

IMEC validated the VAM flow by propagating commercial TSMC 45nm variability data to estimate performance and energy for an ARM926 processor. The VAM output was used to optimize the processor before manufacturing using a commercial tool flow.

"Up to now, most variability characterization work is done internally at IDMs on own technology and IP blocks. However, with the move to fabless and fab-lite companies, we want to bridge the gap between foundry and fabless companies on design-level impact of using most advanced semiconductor technologies," said Rudy Lauwereins, vice president of nomadic embedded systems at IMEC."

Related articles:

Qualcomm joins IMEC TAD design program

Achieving yield in the nanometer age

True design-for-manufacturability critical to 65-nm design success






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