The age of globally accessible, real-time information is upon us. One of the most noticeable driving factors for the semiconductor industry is the need for ubiquitous access to information on any platform, at all times, anywhere on the globe. Computers, mobile electronics, wireless and data storage have therefore emerged as highly energized markets, with significant consumer and financial momentum.

The need for powerful multifunction devices requires the convergence of complex technologies at "consumer affordable" prices. Although the semiconductor industry has responded with the capability to provide enormous processing power on an extremely small IC, the cost of development for smaller-geometry, multifunction devices is becoming the barrier to continued progress for systems providers, be they small or large.

Business pressures will inhibit the move to ultrasmall silicon processes because of the geometrically increasing cost of failure at fine geometries. These contradictory forces result in a paradigm shift to system-on-chip design. This in turn brings about new design issues related to integration requirements and the available flexibility in certain types of intellectual property. The ability to address implementation requirements very early in the design process will provide a competitive advantage.

For example, a virtual prototype, both logical and physical, must be created when there are more degrees of freedom that allow in-depth exploration with a wider array of implementation choices. This change in design methodology is needed not only to address design complexity and market requirements, but for holding the line on development costs while getting more done with less. As more functionality is combined into a single product (for example, a wireless phone/PDA/GPS device), the more critical it is to address integration long before silicon implementation. Otherwise, schedule delays will add to development cost while reducing profit and product longevity.

Design methodology changes in the past two decades have come about in response to advances in semiconductor technology requiring retooling in order to target a new process. Once again we are seeing such advances, but now the necessary changes in design are being driven by economics and productivity. The cost of development, prototyping and introduction of new technologies with smaller geometries is creating a crisis of economics in the development process. Mistakes in the front end simply cannot be afforded in the back end. Doing it right the second and third time is not economically viable.

Retooling will have an impact on up-front design methods and implementation tools. Companies developing SoCs that take the necessary steps toward establishing the methodology changes needed to analyze implementation requirements early will be more efficient and achieve more predictable results. This will yield the most cost-effective semiconductors while addressing seemingly opposing forces: convergence and reduced time-to-profit.

Ajoy Bose, Chairman, President and Chief Executive Officer, Atrenta Inc., San Jose, Calif.