The paper was issued by the so-called Parallel@Illinois lab, one of two research centers launched this year with a total of $20 million from Microsoft Corp. and Intel Corp. to tackle the thorny problem of how to program future multicore processors. The other center, at the University of California at Berkeley, outlined its research agenda in March. A similar center at Stanford, backed by a handful of computer companies, started work in April.

The 50-page Illinois white paper says it describes "an ambitious research agenda that aims to make client parallel programming synonymous with programming." It includes work "in programming languages, compilers, runtime systems, hardware architecture, tools and formal testing methods, along with research in programming patterns and application domains that are expected to trigger the killer applications of the future."

Specifically the group will plow the ground for a new class of "disciplined explicitly parallel languages" and domain-specific environments. It also wants to define a next-generation compiler that can take data from multiple sources including language annotations and runtime environments at different times in the life of a program.

But perhaps the most interesting section of the white paper is a detailed discussion of a new microprocessor designs to be built from the ground up with the new tools and ease of programming in mind. Indeed, the researchers said ease of parallel programming is likely to supplant performance and power as the leading design focus for tomorrow's microprocessors in a world of many-core chips that need to scale in performance but not complexity.

"We now have a unique opportunity to rethink the entire system stack and develop hardware that is better aligned with the needs of modern software," the paper said. "Over time, we need a fundamental rethinking of concurrent hardware, including how to express and manage concurrent work units, communication, synchronization, and the memory consistency model, in tandem with our rethinking of the best practices for concurrent software."

The group will actually pursue two hardware programs. The first, called Bulk Multicore, is defined as "a flexible substrate with scalable cache coherence, high-performance sequential memory consistency, and an easy-to-use development and debugging environment."

The Bulk Multicore design executes groups of related instructions at a time using an emerging style of atomic transactions described by various researchers including some at Microsoft. The Illinois effort will use so-called hardware address signatures, a set of Kbit-long registers that "contain an accumulation of hash-encoded addresses through a Bloom filter. The hardware automatically accumulates the addresses read and written by a chunk into a read and write signatures, respectively."

The approach gets away from the complexity of global cache snooping mechanisms used today, the paper claims.