Editor's Note: This feature kicks off EETimes' Global Design special on ESL design with additional features, including Abstraction and Control-Dominated Hardware Designs from John Sanguinetti, CTO of Forte Design Systems, as well white papers and other related links embedded below. Enjoy!

Electronic System Level (ESL) design is a 21st century phenomenon. Although other disciplines that have used computer-aided-design methods have done system-level design for years, electronic designers have begun to employ this method only recently. From the very beginning of the industrial semiconductor era, now over fifty years old, engineers have paid more attention to structures in silicon than to system architecture. Methods have grown bottom-up, from mylar strips to gates, to registers, to functional blocks. EDA tools have naturally followed the same evolution.

The phenomenal progress of semiconductor fabrication processes that in general allowed engineers to double the number of transistors on the same silicon area every other year or so, known popularly as Moore's Law, made it possible to increase the complexity of designs that could be implemented on the same die. The size of designs first outgrew what a single human brain could comprehend when considering only logic gates, and finally what could be described using register transfer level (RTL) methods. What is not often remembered is that it took approximately 25 years for engineers to begin using hardware description languages to design ICs, and approximately another 25 years before the first use of system-level languages.

ESL really began with the introduction of the SystemC language by Synopsys in 1999. It took three or four years for the ESL market to establish itself and begin to show some financial results. The problem was a lack of automatic connectivity between system level and RTL descriptions. Engineers used languages like C, MATLAB or even SystemC to evaluate design choices at the algorithm level but then had to re-implement the design in RTL using a hardware description language (HDL), such as Verilog or VHDL. Since manual reimplementation was prone to errors, the utility of ESL tools was significantly diminished. EDA vendors have now fixed the problem, and designers have the choice of a number of tools that reliably produce HDL code from a system-level description.

"Now that the ESL methodology has become main-stream the changes are coming fast and furious," said Gary Smith, a consultant who has followed this market segment since its inception. According to Smith, this year, the major impact has been made by the introduction of multi-domain tools. "I mentioned last year that some of the ESL tools were general purpose in nature but the available libraries kept them in a specific domain. It has been fairly easy, although time consuming and expensive, to target these tools to the other domains as The Mathworks has done with its Architect's Workbench. Now we have ESL synthesizers from Forte Design Systems and Cadence that target both the Algorithmic and Control logic domains. Because of that we are moving away from the three domains (algorithmic, processor/memory, and control logic) view of ESL to a more traditional look at the methodology. The ESL methodology is indeed maturing."

System-level languages

When writing about languages for system-level design, it is important to distinguish between languages that are used to validate algorithms and languages used to simulate the implementation of circuits. In fact both C and MATLAB are high-level languages that have been used by designers to develop and evaluate algorithms meant to be implemented in electronic hardware. Both languages have seen their heaviest use in communications applications, and in fact MATLAB has been for years the leading language used for DSP-based design.

Synopsys was the first EDA tools vendor to introduce a language specifically intended for system-level design. Its development was primarily guided by the belief, later mostly invalidated, that a system-level-design language must be usable by both hardware and software engineers. Since C, or more precisely the C++ language, is the most popular programming language, Synopsys chose it as the basis for its hardware system-level language. C++, though, has characteristics that make it a bad choice for hardware design: it is sequential, has no concept of time, and has constructs that have, at least for the moment, no corresponding hardware primitives, like pointers for example.

Using the capabilities of C++, Synopsys developed SystemC. SystemC can be described as a dialect of C++, since it uses the same syntax of C++ but extends the semantics of the language to allow engineers to describe hardware behavior and structure. Although Synopsys, having learned from the language wars between VHDL and Verilog, put the language in the public domain, it took about one year before SystemC was accepted by the other major EDA vendors.

The formation of the Open SystemC Initiative (OSCI) in 1999, has given a significant positive boost to SystemC. Not only have almost all vendors active in the ESL market provided support for the language, but OSCI has continued to improve the language and added the concept of Transaction Level Modeling (TLM) to it. This mechanism alone is responsible for a large increase in the adoption of the language by designers.

In 2006 < a href="http://www.Accellera.org">Accellera released a new version of VHDL that incorporates many features that enhance the language applicability to system-level design. That version was submitted to the IEEE for standardization, and that process ended successfully in 2008. The new official IEEE VHDL specification will be available in print later this year. The new version includes the Property Specification Language (PSL), the VHDL Procedural Interface (VHPI) mechanism, support for both fixed and floating point arithmetic and other language specific extensions.

Designers using Verilog for RTL design have also been given a system-level design tool in the form of SystemVerilog. SystemVerilog is a separate language that incorporates Verilog as a subset with the aim of making it as easy as possible for Verilog users to adopt a new language.

There are also efforts toward developing and standardizing other, less familiar languages. The Design Automation Standards Committee (DASC) of the IEEE has two active working groups: one for Rosetta and one for Esterel. Rosetta is a language that is being built from scratch using very modern system design concepts, but the work is not finished and it is questionable if the working group will be able to meet a window of opportunity that would ensure wide acceptance.

Esterel is a system-design language that has been used, mostly in Europe for many years. Standardization of the language will certainly benefit its present users and may extend its acceptance by system designers. But, once again, the rapid growth in the use of ESL languages that have already achieved standard status will constrain the acceptance of the new language.