Ninety-nanometer design is poised to revive the EDA industry in 2004. The gate explosion in standard-cell-based IC design will continue, with designs over 5 million gates becoming commonplace as processes move to 90 nm and below. Performance pressures along with shrinking design cycles continue to raise challenges for timing closure. Substantial EDA retooling will be required, and products that enable the automatic creation of custom-crafted, design-specific cells will begin to take off.

The only way for design teams to achieve timing and design closure within tight project deadlines for 90-nm designs is to break away from the artificial barriers and limitations of today's standard-cell libraries. Designers have already taken the first step toward this type of design optimization. They have already begun implementing handcrafted "tactical" or "flex" cells, which are derived from clusters of existing standard-cell library elements and optimized at the transistor level. Use of these cells has already resulted in improvements of 15 percent over existing core processors, and is contributing to a growing movement toward this methodology.

To get to 90-nm silicon, the IC industry needs to bring custom performance to standard-cell design. This is both a technical necessity for IC design companies and an economic opportunity for EDA vendors.

Timely innovation supporting the emerging trends is still the best way for EDA vendors to successfully grow their businesses and fund the ongoing research and development that is critical to the health of both the EDA and the semiconductor industries.

Those EDA vendors that can deliver stable, high-value products that automate the flex-library-cell creation process sufficiently to quickly make it viable to mainstream IC design organizations will flourish in the 90-nm design retooling phase.

Jay Roy, Chief Executive Officer, Zenasis Technologies, Campbell, Calif.