If we expect the electronics and EDA industries to have long-term robust growth, we need a constant stream of funding for really novel ideas so that the end applications exist to drive growth in future years. The high price of ASIC development has stunted such investment.

The next big thing could easily be a crazy idea for which no one in their right mind would fund an ASIC. If the novel idea does not fall within the cost/performance/power bounds of an FPGA, adopting a structured-ASIC or platform-ASIC approach might lower the risk of funding it. Structured and platform ASICs don't just lower NRE charges; like FPGAs, they also involve a dramatically reduced set of design tasks. Tasks like test insertion, clock distribution, power grid design and checking, layout DRC, signal integrity and timing closure are addressed with a combination of tools and silicon architecture so that the engineering team can avoid an unnecessary risk of errors and focus on the application instead of the silicon issues.

The advantages of structured and platform ASICs will jump with the introduction this year of 90-nanometer parts. Many design teams plan to remain at 180-nm and 130-nm processes for new designs because the silicon issues at the lower geometries are too scary. Between the silicon vendors and tool vendors, however, we can presolve these issues. There is a performance and density cost for adopting a structured approach to the problems, but the raw technology difference between 90 and 130 nm will make up for it.

Structured and platform ASICs will also move ahead on the process curve and stay ahead of most standard-cell designs, just as FPGAs have. After a product is a success, costs can be brought down based on a standard-cell flow.

With the emergence of structured and platform ASICs, we have laid the foundation for a low-cost path to production that will enable the broad product innovation the industry needs for growth.

Ken McElvain, Co-founder and Chief Technical Officer, Synplicity Inc., Sunnyvale, Calif.