Sang Wang, Chairman and Chief Executive Officer, Nassda Corp., Santa Clara, Calif.

Entering the nanometer era, designers need more prudent approaches if they are to succeed in delivering highly complex products using progressively smaller-geometry process technologies. The semiconductor industry's first concern is the increasing cost of development. With the price tag of a 130- or 90-nanometer system-on-chip product running between $20 million and $50 million, there is little margin or tolerance for errors. The high cost has also driven down the number of design starts for most large semiconductor companies.

Overall, the deep-submicron approaches and flows are generally not adequate or reliable in handling nanometer designs, especially high-end products. These approaches and flows must be enhanced if they are to satisfy the more demanding nanometer requirements. Clearly, a hierarchical approach and parallel computing resources at various stages of the design flow are needed to handle large circuit sizes and the huge number of elements in nanometer circuits. Timing management and power optimization must be maintained throughout the flows. Signal integrity from coupling capacitors and the supply voltage IR-drop variations must be analyzed in detail to avoid layout iterations.

The behavior of mixed-signal and memory intellectual property must be accurately characterized and the IP smoothly and flawlessly integrated into the surrounding circuits. Device reliability for hot carriers and temperature bias instability must be analyzed and ascertained at and below 90 nm. Furthermore, full-chip simulation and analyses, design-for-manufacturability and design-for-yield will be key areas for improving the overall nanometer flow. Future semiconductor success will depend on the newly enhanced nanometer approaches and flows. Those EDA vendors that can cross the threshold and deliver full-chip capabilities in verification and analysis at the nanometer level will thrive and win in the growing nanometer market.