The electronics industry has conspirators aplenty in , keeping it off balance and out of sorts. Start with technical uncertainty — that is, new process technologies — and move to the task of piecing intellectual property (IP) onto a chip. Look next at the implementation model, the disaggregation of the design chain, then try to determine how to make money. We're concerned about product life cycles, application and silicon complexity. Frame this against a backdrop of an uncertain world economy.

We're an industry fraught with choices and complicated decisions. The decision to design a chip offers multiple implementation options. Selecting the optimum approach requires technical and economic analysis and IP that works. Each choice has advantages and a magic set of operating points that makes it ideal for a particular product. Unfortunately, it isn't the well-understood volume driver of yore — the PC silicon that can advance Moore's Law alone. The industry knew what to build and was able to aggregate. In the new consumer economy, customers are fickle and always want new features. Product life cycles are product nanocycles.

We're at an inflection point where we're on plan with Moore's Law, but the economics haven't caught up. The industry needs a way to analyze the economics of Moore's Law and drive the design process. Everything affects everything in this fast-paced world. Bigger chips mean more use of IP. Sometimes as much as 75 percent of the die size is consumed by purchased or reused IP. In turn, for every piece of memory IP sold, there is an electronic design automation (EDA) system for memory design that is not sold. Still, more-advanced chip integration EDA software is needed.

Semiconductor products are about economics. Shortening product life cycles have made the up-front capital investment harder to recover. Amortization of the up-front costs is making non-bleeding edge technologies the right choice for short product lifecycle applications.

No single approach or application helps design teams make economic tradeoffs. Instead, suppliers need to service multiple applications and implementations. What is certain is that the use of third-party IP, especially hard IP, will grow rapidly, like the component business of the last 30 years. All aspects of the supply chain — especially, foundries, EDA, IP and design services — must get along to get more designs into production.

It won't be long before we see more IP-aware, economically savvy design tools. Decisions into product viability are no longer held by implementers. Success or failure is determined up-front in specification, architecture, technology selection and IP. Bad early economic decisions are being taken to reality by implementation teams. Up-front estimation is no longer a 50 percent game. It's a game of five to 10 percent allowable error in cost, size, yield, power and leakage. For this to work, knowledge of IP, library behavior, power and density must all be available in new estimation tools at the earliest phase of a project.

The goal, then, for the second half of 2004 and beyond is to know the design before its implementation. Well-planned journeys to chip success guided by a "chip global positioning system" are the future of our industry in 2004.

J. George Janac, CEO and Chairman, Giga Scale Integration Corp., Cupertino, Calif.