Each generation of silicon process node shrinkage results in significant increases in design cost: at least 60 percent for engineering and 40 percent for manufacturing. The only viable way of lowering these costs while improving overall turnaround time is by using a highly integrated design tool suite that eliminates iterations and addresses timing, area, power, signal integrity and yield concurrently, not just timing closure.

At Magma, we have found that a properly designed EDA tool suite, using a unified data model and embedded concurrent analysis and design parameter optimization, can result in reductions of 50 to 90 percent in chip turnaround time, 10 to15 percent in die size and 15 to 35 percent in power. The right EDA tools can mean the difference between profit and loss on a chip development program.

Concurrent optimization lets the designer solve problems that affect multiple design parameters. For example, fixing problems caused by IR drops on the chip, which can cause intrachip variation in supply and ground voltage levels, results in both improved signal integrity and timing performance.

Increasing design efficiency through integrated design tools and embedded concurrent analysis and optimization saves money in several ways. On the design side, efficient design reduces the iterations between separate design operations such as synthesis and place-and-route. In addition to saving design time, design efficiency also increases the probability of first-time silicon success. With an integrated tool suite from a single vendor, the chip's design team can comprise fewer members, since running an integrated suite is simpler than combining and running point tools from multiple EDA vendors. Another economic advantage of a single-vendor integrated suite is the need for fewer tool licenses. Finally, an EDA suite from a single vendor is better equipped to deal with new design implementations, such as structured and platform ASICs. These implementations are becoming increasingly popular, since they reduce design time, design iteration loops, risk and cost compared with traditional ASIC and ASSP design flows.

Manufacturing costs also profit from a design automation flow that addresses total design and embedded optimization. Close coupling of physical-layout and logic-synthesis operations results in better chip layout and a smaller and less expensive chip. Yield is also increased because a smaller chip results in fewer vias and shorter average wire length, both of which reduce yield loss.

Another benefit of concurrent design parameter optimization is reduced power dissipation. This has several benefits, including less power-induced performance variation across the chip, which enhances chip yield, and the use of less expensive IC packaging, which reduces both chip and system cost.

Enhancing design-for-test results in higher yield through manufacturing test, another cost reduction advantage. In addition, optimized test sequences reduce the time it takes to test the chip on expensive test equipment, further reducing manufacturing cost.

Rajeev Madhavan, Chairman and CEO, Magma Design Automation, Santa Clara, Calif.