After analyzing state-of-the-art DRAM devices from the Korean manufacturers Samsung and Hynix, Semiconductor Insights gave Micron its turn under the magnifying glass. With the help of advanced imaging techniques, SI analyzed the process technology used to fabricate Micron's newest 1-Gbit DDR2 50-nm SDRAM and is now ready to reveal some of the design trends introduced by the North American DRAM manufacturer.

The latest DRAM offering from Micron can be technically defined as a true 50-nm product. This was confirmed by the accurate measurement of the device's wordline half-pitch. By comparison, the half-pitch dimensions of the Samsung and Hynix devices are respectively 58 nm and 54 nm. It is now established that the patterning of 50-nm-size features is pushing the limits of standard 193-nm "dry" photolithography, even with the use of resolution-enhancement techniques. To produce these densely packed structures, an advanced lithography approach is required, such as immersion lithography or double patterning. Interestingly, Micron appears to be using advanced lithography techniques not only for the wordline definition but at other critical layers as well. For example, the minimum metal 2 line pitch observed on the Micron chip is 150 nm. This critical dimension is on par with what is seen nowadays in advanced logic processes such Intel's 45-nm technology. The move to immersion lithography at multiple layers would represent a formidable capital investment for Micron, and it is more likely that an immersion-light approach is adopted at this time. Micron is keeping quiet about whether or not they are using immersion lithography in production.

Micron's 50-nm wordline half-pitch results in the smallest cell size ever seen in a DRAM device. Micron first introduced its 6-F² cell design at the 0.11-µm technology node (analyzed by SI back in 2004), and this same proven layout is still in use at the 50-nm node. The 6-F² cell from Micron is rectangular and measures 3 F in the bitline direction and 2F in the wordline direction, where F is the half-pitch of the respective lines. In this design, an isolation line, or dummy wordline, is used to isolate two adjacent cells. The remarkable aspect of this design is that by removing the dummy wordline and tilting the active areas by 45°, a 4-F² layout could be obtained. It remains to be seen if a sufficient capacitor could fit in such a small cell or if the active regions could be properly isolated from each other. However, Micron's current cell design has the potential to become the first to be converted to the smaller 4-F² size.

It must be noted that Micron's cell size does not exactly correspond to the nominal 6-F²; size where F = 50 nm. This is because the bitline pitch is slightly relaxed. Hynix achieves a smaller 54-nm bitline half-pitch in their device; however, the use of a conventional 8-F² cell layout results in a cell size that is effectively 33 percent larger. Overall, Micron's 1-Gbit DDR2 die size is 8 percent smaller than Samsung's corresponding device and 11 percent smaller than the Hynix die. In theory, Micron could achieve an even larger die-size difference, but Micron's die efficiency (i.e., the size of the memory cell array versus the total die size) was calculated to be slightly lower than the two Korean devices.

In a modern stacked-capacitor DRAM device, the structure of the storage capacitor can be thought of as a vertical tube made of titanium nitride (TiN) with an aspect ratio of about 10:1. To maximize the capacitance value of the cell in high-performance DRAM devices, it is important to form the capacitor dielectric and top electrode, or cell plate, on both inner and outer surfaces of the tube. To achieve this double coverage, the dielectric material surrounding the storage nodes needs to be removed during the fabrication process. This step normally results in an array of densely populated, fragile tubular structures that have no lateral support. To improve the mechanical stability of the storage capacitors, Micron is using a thick nitride spacer layer at the top of the storage nodes. It's easy to visualize such a structure. Just think of those handy plastic rings used to hold a six pack of aluminum cans of your favorite beverage. In this analogy, the aluminum cans would be the storage nodes and the plastic rings are the nitride spacer that keeps the nodes apart from each other. This idea is neither new nor exclusive to Micron since Samsung does something similar. However, Micron's implementation is slightly more elegant and efficient in that it removes the dielectric material only in the memory cell array and leaves it intact in the periphery. This is achieved by properly isolating the array area from the periphery and by creating openings in the spacer layer so that the dielectric material present underneath can be removed. The use of this storage-node spacer adds to the overall complexity of an already complicated DRAM process, but the improved stability and yield no doubt compensate for the added cost.

A major change to Micron's process flow at 50 nm was to switch from hafnium oxide as the main component of the capacitor dielectric to zirconium oxide. Zirconium oxide has a higher dielectric constant and lower leakage than hafnium oxide and now represents the de facto standard for advanced DRAM devices. This change from Micron highlights the need for DRAM manufacturers to extract the maximum capacitance from the current storage-node design without having to make significant changes to the physical size and shape of the capacitors.

Micron has been using copper metallization for the upper interconnects for many product generations. For the first time at the 50-nm node, a second manufacturer (Elpida) has announced the integration of copper in a DRAM device. However, one process feature that still distinguishes Micron from the rest of the DRAM crowd is the use of raised source and drain (S/D) regions formed by selective epitaxy. The elevation of these regions above the substrate allows shallower S/D profiles within the substrate, which, in turn, improves the performance of short-channel MOS transistors. The raised S/D regions probably also benefit the recessed channel array transistors (RCAT). RCAT structures are now widely adopted by DRAM manufacturers to help reduce leakage by effectively increasing the size of the transistor channel in the tightly spaced memory array. By having the S/D partially moved above the substrate, Micron can achieve the same leakage-reduction effect with a shallower RCAT trench structure. In fact, the RCAT trenches in the Micron device are only half as deep as the ones used by Samsung.

With their latest 50-nm process technology, Micron seems to have struck the right balance between investment in new technologies (advanced lithography techniques, improved high-k materials) and conservative design decisions (proven 6-F² layout, no scaling down of gate dielectrics). Their balanced approach positions Micron well to keep up with the ITRS roadmap for the technology nodes to come. At the same time, it will help them control production costs while gradually improving yield and reducing cycle time, which are of the utmost importance in the fabrication of DRAM products.

Carl Wintgens is senior process analyst at Semiconductor Insights, which specializes in analyzing semiconductors.

Acknowledgements: Special thanks are owed to Lisa MacElwee at Semiconductor Insights for the superb SEM images.