The 45-nm technology node is coming at us faster than you can spell M-O-O-R-E-'S L-A-W. It's a safe bet that the verification challenges are going to be an even greater menace than they are now because, as technology process nodes shrink, the gate count in designs rises. And, rising gate counts means escalating verification nightmares.

Further still, the amount of time budgeted for verification in a single project cycle--currently estimated at 70 percent--may increase even more and even more drastically. And, the increased quantity of embedded software content, already a huge and complicated factor in chip design, will force engineering managers to consider verification from the project's outset.

What's a project team to do when the verification workhorse known as simulation has run out of gas for anything longer than basic interconnectivity tests?

First rule of thumb when presented with the 45nm verification conundrum: Take a deep breath and exhale slowly. And then reconcile yourself to the fact that verification now must be considered throughout the entire project cycle, from hardware verification, hardware/software integration to embedded software validation.

I often compare testing the latest system-on-chip (SoC) designs and rooting out those pesky bugs to finding a needle in not one, but two haystacks: a hardware haystack and a software haystack. Let's not forget that engineers are proud individuals, reluctant to admit fault or accept blame. They also favor the solitude of their cubicles to the social life of the community. Pride and isolation disrupt the project schedule and have a way of derailing the path to first silicon. The appearance of a design bug could trigger the defensiveness of either the hardware or software team and sets into motion the counterproductive blame game. Ultimately, the unnecessary confrontation will consume precious time and delay tapeout. This means now more than ever engineering managers must develop a rigorous verification strategy at the start of the project.