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Early design verification with virtual system integration and simulation
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EE Times


Embedded and electronic system design teams face the challenge of reducing development time and costs while improving quality, performance and functionality. However, increased system complexity is raising the cost of verification, in some cases to as much as 70 percent of the overall project cost. As verification consumes more time, it eliminates opportunities for engineers to create product differentiation through design optimization and to focus on innovation.

This problem manifests itself differently across industries:

• Engineers at electronics OEMs and suppliers try every possible verification technology, hoping to avoid the re-spin that will halt their race-to-market with the next generation device.

• Automotive and aerospace engineers conduct extensive design and code reviews to confirm software in dozens of embedded processors meets design requirements.

• Industrial automation engineers struggle to design and integrate increasingly complex control and mechatronic systems with hardware prototypes in the lab.

These scenarios share two common problems: the difficulty of determining whether designs and implementations meet requirements; and the waste involved with manual testing and rework. These challenges stem from fundamental workflow gaps across stages of development and disconnected tools used by component design teams. Even if each component is designed well and tested extensively, issues related to requirements and integration are often found towards the end of the development process.



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