As process technologies scale below 0.13 micron, challenges in manufacturing cost-effective new designs are increasing. To address emerging challenges that cannot be resolved through process optimization, comprehensive design-for-manufacturing (DFM) methodologies must be employed throughout the design flow to ensure correct-by-construction, process-aware designs.
A robust DFM methodology must first characterize the target process capability applied to design-relevant topologies, defining an optimal resolution enhancement technology (RET) strategy for these target topologies. For instance, in early development of SRAM bit cells, the asymmetric response is the result of interaction between bit-cell features and localized process variation. Once variability has been characterized, it must be optimized through modeling and empirical observation.
Experiments investigating variations in bit-cell design are performed to optimize this design element for least variation and greatest manufacturability. Similarly, process capability is characterized for a host of predominant design topologies, including standard-cell effects and place and route algorithms for understanding the optimal layout implementation for the target manufacturing process.
Concurrent with process technology and RET characterization, an optimal DFM strategy employs "best practices" layout guidelines at different stages to capture a layout designer's intent, while providing additional margin for manufacturing. For each case, appropriate process characterization structures, test methodologies and data reduction approaches are required.
Variability can be observed by device properties from a particular device (length and width), as seen across two different, but design-rule-compliant, layout approaches. The selected feature attributes and layout practices employed are critical to achieve optimal product design. Typically, a library of key topologies (or feature combinations) is defined within design rule guidelines and within technology files used by common EDA platforms.
Correct by construction
This specification helps reduce the use of such topologies, and allows identification of these features throughout the design for future optimization or monitoring in-line. For example, DFM approaches seek to limit the use of minimal poly-enclosed gates, minimally enclosed vias and singly contacted lines. Where not limited by space constraints, vias will be drawn with redundancy or supernominal enclosure to provide reduced sensitivity to critical dimension, overlay or defectivity. Similarly, DFM guidelines will identify areas where routing lines can be relaxed in pitch, line width and line spacing.
Finally, a DFM methodology comprehends automated optimization techniques that interface efficiently with the overall product design flow. This includes the ability to codify key layout topologies using available EDA tool capabilities, and optimize these topologies within the particular layout context.
Feature optimization can be achieved through either a straightforward extension of well-known DRC verification techniques or a set of sophisticated requirements that are only partially integrated within a common design environment. In these cases, a patchwork of optimization solutions must be assembled to achieve a correct-by-construction implementation.
Mark Craig and Steve Zika are with Advanced Micro Devices Inc.'s Computational Products Group.
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