The company, jointly owned by Advanced Micro Devices Inc. and Fujitsu Ltd., details its plans in a road map to be released today. It carries Spansion's NOR flash devices from the 110-nanometer, 512-Mbit devices already in production through the 45-nm process node and to densities of 8 Gbits per die, nearly overtaking the NAND flash road maps of the company's competitors.

"We are currently producing 512-Mbit NOR devices," Spansion president and CEO Bertrand Cambou said. "We already have material in manufacturing for a 1-gigabit NOR device, and our near-term road map will carry us to 8 gigabits."

The road map sets forth two startling points: that flash has a future at 45 nm and that NOR memories can overtake NAND densities in a matter of years.

Clearly, Spansion believes that flash memory will be entirely viable through at least the 45-nm node. "In fact, we have 45-nm test chips in the Submicron Development Center here in Sunnyvale already," said John Nation, Spansion's division marketing manager.

The road map also puts NOR flash on a trajectory to intercept the density and cost per bit of NAND flash by about 2007. That's significant because of the way today's flash market is segmented. NOR devices occupy lower-density applications and applications in which durability — the ability to endure thousands of read/write cycles without error — and data retention are critical.

Code storage is one example. NAND devices have had a firm lead in density — up to a factor of 16 — but suffer from higher bit-error rates. That has left NAND dominating data storage applications where error-correcting codes can be employed or where bit-level errors can be tolerated. Getting NOR devices, with their high reliability and flexible operating modes, to NAND-like densities could change the way architects approach system design.

Density without drawbacks
"At the 1-gigabit level the die size for a full-feature 90-nm NOR flash chip using [Spansion's proprietary] MirrorBit technology is similar to the die size for NAND flash, and the manufacturing cost per yielded die is considerably less," Nation said. "We are coming to a point where users can get the density they need for data storage applications without having to accept the slow read times, complex operation and poor reliability of NAND."

Cambou said the lab had demonstrated the feasibility of multilevel cells, which would make it possible to store 4 bits of data in the dual-transistor MirrorBit cell.

Spansion's road map stands in stark contrast to the NOR plans announced by other flash vendors. Toshiba, for instance, said it plans to have 256- and 512-Mbit NOR devices fabricated in 90-nm, 1.8-volt technology, but not before mid-2005. The company does not show any larger NOR devices on its road map yet.

But catching NAND in density won't be easy. Toshiba's single-level cell NAND road map calls for 2-Gbit devices this year, followed by 4 Gbits in early 2005 and 8 Gbits in mid-2006. The company expects to simultaneously announce both single-level cell and 2-bit/cell devices at each step. That would keep the largest Toshiba NAND devices comfortably ahead of the largest Spansion NOR devices, at least in the near term.

"We have three teams working in parallel on the 90-, 70- and 55-nm technology nodes," said Brian Kumagai, Toshiba's NAND business development manager. "The 2-Gbit single-level NAND device and the 4-Gbit multilevel-cell device are now both in production, and in the first quarter of next year we will bring out the 70-nm, 8-Gbit single-level chip."

That device is now taped out and running on a pilot line, added Scott Nelson, also a director of business development with the company. "It is coming along similarly to any other new memory design. Nothing alarming has turned up."

Cambou attributed the breakout acceleration in NOR density to the rapid maturity of the MirrorBit process. Michael Van Buskirk, Spansion's CTO and group vice president of engineering, added, "There are inherent advantages in the MirrorBit cell that make it both more scalable and more manufacturable than a floating-gate cell."

The fundamental difference is that the MirrorBit cell does not use a floating gate for charge storage. In a conventional flash device, NOR or NAND, data is stored on a polysilicon gate structure sandwiched into the gate oxide, usually near the edge of the control gate. Charge is moved onto and off this electrically isolated gate by some combination of Fowler-Nordheim tunneling and hot-electron migration.

The MirrorBit cell, in contrast, does not store a charge on a conductive polysilicon floating gate. Instead it traps a charge in an insulating nitride layer sandwiched between two thin layers of conventional oxide. In effect, the mechanism exploits the charge-trapping phenomenon that has been the nemesis of memory cells since the early days of the industry.

The cell uses techniques and voltages for writing and erasing similar to that of the floating-gate cell. But it moves considerably less charge, so it can potentially write much faster. "If the circuit is properly prepared for writing — and we are not disclosing what exactly we mean by that — then the MirrorBit cell is inherently faster-writing than the floating-gate cell, even than the floating-gate cell in NAND configurations," Van Buskirk said.

Yield comparisons
The simple sandwich structure is also inherently planar, and far less sensitive to both contact defects and alignment problems than the floating-gate cell, he said. Spansion, which makes both floating-gate and MirrorBit devices, said MirrorBit arrays reach production yield levels three to six months earlier than do floating-gate arrays at the same process node.

In addition to the unique charge storage device, the MirrorBit cell contains two independent storage transistors, storing 2 bits in each cell. That gives it an area advantage over conventional single-bit cells. By employing multilevel storage on each transistor the MirrorBit cell can reach 4 bits per cell — a fact that Spansion plans to exploit in future products.

An important attribute of the MirrorBit technology, Nation said, is that it uses essentially a standard logic process, with only thehe nitride layer added. There is no second poly, and because the structure is planar there is no compatibility problem with the complex metal stacks used in ASICs. That makes it relatively easy to add dense, high-performance logic to a MirrorBit chip.

"This is just the opposite of the conventional strategy for embedded flash in a logic process," Cambou said. "With floating-gate flash technology, process engineers have to painstakingly integrate a flash module into a mature logic process. It adds lots of masks and cost. That's why you typically see embedded flash offered in a process that is one or two generations behind the leading edge."

Spansion, in contrast, is actively adding significant amounts of logic to its flash process. This trend started long ago, when flash vendors began to build write controllers, read and write buffers and other logic to the flash chips to conceal their basically complex operating states from the user. The trend continued as vendors added complex page structures, much larger buffers and other tricks to mask the slow write times of multilevel-cell devices.

"In the near future, you will see the multilevel cell chips closing the performance gap on single-level cells," Toshiba's Nelson predicted. "The change won't come from a fundamental improvement in cell performance — that's physics — but from advances in page sizes and write-mode features."

Spansion's Nation said that with MirrorBit's inherently logic-friendly process, his organization can go further still. "The ability to put lots of fast logic on the die allows us to talk with customers, and with suppliers of logic chips, about how they'd ideally like to see their system partitioned," Nation said. "We are looking at functions like encryption, advanced sector protection schemes and even digital rights management that maybe really belong on the flash chip."