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Unified transistor modeling on tap for IEDM
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EE Times


Portland, Ore. — A unified model for predicting the long-term reliability of semiconductors will be described next week at the 50th annual IEEE International Electron Devices Meeting.

The technique, which simultaneously foretells negative-bias temperature instability and hot-carrier injection, could potentially save chip makers tens of millions of dollars annually.

As nanoscale transistors shrink, the atomic-scale bonds that keep semiconductors reliable become fewer and fewer, making mean-time-to-failure predictions more important than ever. But to predict long-term reliability today, separate models must be maintained for the two primary causes of failure in semiconductors: negative-bias temperature instability (NBTI) and and hot-carrier injection (HCI).

"Today, reliability is becoming much more important, because dimensions are getting so small," said Purdue University professor and semiconductor researcher Ashraf Alam, who will describe the details of a unified model at IEDM, to be held Dec. 13 to 15 in San Francisco (www.his.com/~iedm). "But only recently has reliability begun percolating into the design phase — rather than just being an afterthought. Our unified model will make it much easier for designers to measure reliability of new device architectures."

Alam is a veteran semiconductor researcher who formerly worked at Agere Systems' Bell Laboratories (see www.eetimes.com/showArticle.jhtml?articleID=18402484).

He performed the current work with Purdue doctoral candidate Haldun Kufluoglu.

"This model will work with all types of new devices, such as silicon nano-wires, enabling designers to try different options and know how they affect reliability over time — even before they are fabricated," Alam said.

Up until now, NBTI and HCI have been considered separately. Generally, reaction-diffusion models have been used for the NBTI predictions but could not be made to work for HCI. Now Alam and Kufluoglu think they have found a way to integrate NBTI and HCI into the same reaction-diffusion model.

"I don't want to reveal the details before giving our IEDM paper, but the general idea is that geometry makes the difference," Alam said. "NBTI appears to use one-dimensional diffusion, whereas HCI's diffusion is two-dimensional, which explains the different rates."

Other researchers failed in uniting the two, he said, "because they did not differentiate between one-dimensional and two-dimensional diffusion."

When failure occurs
Chips usually fail not because the silicon itself diffuses away, but through the diffusion of the hydrogen atoms that fill the gaps between each layer of silicon semiconductor and silicon-dioxide insulator. Both NBTI and HCI cause that hydrogen — needed because silicon and silicon dioxide have different lattice dimensions — to diffuse away, albeit at different rates. Now, Alam and Kufluoglu have forged a single diffusion-reaction model that predicts both.

"As we approach the end of the International Technology Roadmap for Semiconductors, designing reliable systems with unreliable components — degraded by NBTI and HCI — will become more of an issue, and predictive modeling such as ours will help in that regard," said Alam. "For the first time, we have been able to connect HCI and NBTI."






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