Last year, by canceling capacitive loading with integrated inductors, IBM and Columbia solved the jitter and skew problems of distributing gigahertz to terahertz clock signals in a prototype chip that retrofitted IBM's current clock distribution circuitry. This year, the IBM-Columbia design will feature a resonant oscillator solution that, if successful, will redefine the way clock distribution is done on high-end IBM processors.

"I can't tell you the details of our new design before the ISSCC paper, except to say that we looked at everybody's resonant clocking techniques and have come up with a solution which we think will change the way clock signals are distributed on high-end processor chips," said Steven Chan, an EE at Columbia University. Chan works under EE and professor Ken Shepard in cooperation with physicist Phillip Restle at IBM's T.J. Watson Research Center (Yorktown Heights, N.Y.).

So far, three test chips have been fabricated. The first was last year's traditional clock distribution circuit, modified to be resonant. Since then, two further chips have been designed at Columbia University that have been shown to reduce both power and jitter by approximately a factor of three.

Resonant clocks solve those problems with integrated inductors that cancel capacitive loading, thereby quelling jitter and skew. And because energy is recycled, power requirements are reduced.

Inductors tune the circuit to the frequency of the clock-up to 5 GHz in current IBM-Columbia test chips-and keep the clocks in sync across a chip. Coupled LC oscillators providing constant phase and constant amplitude will be described in the ISSCC paper as the easiest way to implement resonant clocks on today's high-end IBM processors. Those processors use a large number of clock grids driven by small (1.15 mm square) wiring trees, enabling integrated spiral inductors to cancel the capacitance of each tree and thereby transforming a nonresonant network into a resonant clock distribution net.

IBM's distributed differential global clock oscillator was designed into two test chips, one in a 90-nanometer and the other in a 0.18-micron, 1.8-volt CMOS technology. Measuring 2 x 2 mm, the resonant clock network had a tank Q of 4.3, had tenfold less jitter and used nearly three times less power than conventional clocks.