Now available On-Demand. On September 16th, EE Times brought to you the third in its Virtual Conference series titled: System-on-Chip: Designing Next Generation SoCs. Now available via On-Demand, this virtual conference explores the challenges faced by developers of ASIC- and FPGA-based SoCs, including an in-depth look at the state of chip design economics, the quest for plug-and-play intellectual property, the state of the verification bottleneck, and the need for better integration between analog and digital design flows.
This conference will be of interest to hardware and embedded software management, including systems architects, system designers, embedded system designers, and ASIC- and FPGA-based SoC developers.
Tracks (and included product categories/technologies):
- The Economics of Chip Design: EDA and FPGA vendors, IP vendors and design service providers.
- Verification: Verification tools, verification acceleration tools, hardware-software co-verification tools, tools for Open Verification Methodology and Statistical Timing tools.
- Intellectual property: IP vendors, design service vendors, ASIC vendors and FPGA vendors
- Analog/Digital Integration: Analog design, circuit simulation tools, device modeling tools, Rapid Prototyping Platforms, RFIC simulation tools, Signal Integrity Analysis tools, Analog/mixed-signal verification tools, Analog/Digital co-simulators, Transistor-level debugging tools, System-level design tools, Verilog/VHDL simulation and verification tools, and Mixed-signal FPGAs and design tools.
