Semiconductor Memories: Pete MacWilliams
DRAM journey nears its goal

It's before 8 a.m., and Intel Fellow Pete MacWilliams is charging through the lobby of Tokyo's Imperial Palace Hotel, dressed smartly in a navy blue suit, set for a day full of meetings. The fact that today is Culture Day, a national holiday in Japan, makes scant impression on MacWilliams. Holiday or not, he and his peers at Japan's chip companies will be spending the day hammering out details of what is perhaps the most significant transition to new PC DRAM technology the industry will ever make. And it's only a few quarters away.

If a book on the history of DRAMs were ever to be written, 1998 would surely mark a pivotal year. It was in the last 12 months that the process of reaching gradual consensus on which DRAM technology will succeed the previous generation has come to an end, driven by a strong-willed microprocessor vendor with deep pockets and a determination to make sure DRAM won't trip up the overall performance of the system. It was also this year when the cool-headed, methodical world of DRAM development was transformed into a hotbed of debate.

MacWilliams has closely charted the course of memory technology for Intel Corp. platforms since 1995, but he had his hands particularly full in 1998 shepherding the shift to PC-100 DRAMs and preparing the industry for a more significant move to Direct Rambus DRAMs only a year later. A technologist to the core, MacWilliams found that learning to be a good business negotiator was now part of his job description.

"It's been a struggle," said MacWilliams. "I'm a technology guy, and sometimes I have to remind myself that technology is just one aspect of the problem."

Over the past several years, MacWilliams has worked with DRAM manufacturers to develop a road map for cache and DRAM technologies for future PCs. He joined Intel in 1979 as a design engineer after receiving his MSEE from U.C. Berkeley, and was named Intel Fellow in 1990. During his career at Intel, MacWilliams has been deeply involved in the development of bus and chip-set architectures.

Despite a few close calls, MacWilliams says the transition to PC-100 synchronous DRAMs has been made with hardly a hitch. The move to Direct Rambus will be more challenging. Nevertheless, MacWilliams and his team of a dozen or so engineers who make up the memory-enabling group at Intel have managed to cut through the wails of protests over Rambus manufacturing costs, heat concerns, possible packaging shortages and added licensing and royalty fees, holding firm to the plan to drive Direct RDRAM into the market in 1999. But not without making some concessions along the way.

Essentially, the problem boils down to this: how to prepare for a an ultrafast DRAM with a radically new interface design that will add cost and require new infrastructure, and do it only one year after the introduction of a more conventional memory architecture that will continue to serve a large portion of the market for years to come.

Until a few years ago, such a question would not have arisen. For decades, the memory industry has been operating on the notion that raising density and reducing process technology were the primary concerns. Speed and bandwidth, while important, usually took a backseat to size and cost. Only workstations, mainframes and servers required the fastest DRAMs, and they were treated as a niche.

"The DRAM industry isn't used to this kind of transition," MacWilliams said. "Their business model has been largely about the evolution of process technology and density."

That changed in 1995 when Intel, reaching the peak of its stature as the premier supplier of X86 MPUs, noticed that years of limited gains in DRAM performance would soon take a toll on the overall platform. Traditionally, improvements made to the platform architecture managed to bridge the gap: adding cache memory to the 386, writeback cache and 64-bit memory interface to the Pentium, or backside cache and SDRAM for the Pentium II.

"These approaches were running out of steam for the volume desktop, as we saw with the introduction of EDO [extended-data-out DRAM]," MacWilliams said. "A closer look identified a basic change in I/O and applications that would further increase memory-performance demands."

As such, MacWilliams and his peers at Intel took on memory bandwidth with a new sense of urgency. The company first intervened during a 1995 shortage of EDO DRAMs by distributing data sheets with a common spec to help vendors improve their yield. The next year, the Santa Clara, Calif., chip giant jumped in as an arbiter of a debate about a subset of a specification for 66-MHz SDRAMs, which some vendors wanted to pursue in hopes of reducing their test costs.

Following the so-called SDRAM "lite" fracas, Intel decided to assume a more active role in the next-generation technology by defining the PC-100 SDRAM spec, everything from the I/O driver parameters to the DIMM layout. And because it oversaw the testing of sample product, Intel's role expanded to that of a pseudo-validation body for the industry. The company said it is not actually qualifying DRAM vendors for PC companies, however.

Despite all the preparations, by the fourth quarter of 1997 many DRAM companies were still not spinning enough PC-100 samples in preparation for the launch of the BX chip set, scheduled for the second quarter of 1998. "With the first parts that came in the fourth-quarter time frame, there were lots of initial problems with vendors not meeting the spec," MacWilliams said.

To stave off a possible shortage of DRAMs, Intel spent more time talking to DRAM vendors and set up a test site at Smart Modular Technologies (Fremont, Calif.) to check for compliance to the spec. "Our goal was to see that the vendor could build at least one compliant part and that our data correlated with their data," he said.

When it came time for production in the first half of 1998, most of those problems had been worked through. "When we got to actual production, it was the smoothest ramp we've ever seen."

A repeat in '99?
MacWilliams hopes to repeat that success in 1999, when the company expects to ship its first Direct RDRAM-enabled chip set for what it calls the "performance PC" segment. Intel has a lot riding on that platform, which will be based on the company's new Katmai processor, with a fresh crop of SIMD (single-instruction, multiple-data) instructions for enhanced multimedia capabilities.

"With Rambus we have a different interface, packaging and testing requirements," he said. "This is a huge change and it needs to be done quickly across many DRAM vendors."

There's some good reasons for MacWilliams to be optimistic. By the second quarter of 1998, LG Semicon, NEC, Samsung and Toshiba had produced their first silicon samples of 72-Mbit Direct RDRAMs, a milestone that has given Intel the confidence to stick to its Q2 chip-set rollout plan. Also, Dell and Compaq have announced they will sell systems based on Direct RDRAMs in 1999, and sources at chip companies have said there is strong interest from other top-tier PC makers such as IBM and Hewlett-Packard. As an added bonus, Advanced Micro Devices Inc. also announced it would support Direct Rambus for its next-generation K7 microprocessor.

Even so, Intel's Direct RDRAM strategy came under close scrutiny as vendors complained that the size of the core would make it substantially larger and more expensive to produce than PC-100. On top of that, vendors would have to pay for new testing equipment and house the DRAMs in pricey chip-scale packaging.

In response to these cost concerns, Intel came up with a contingency plan to offer so-called S-RIMM modules, which have the same configuration as RIMM modules, except they have PC-100 SDRAMs on board. Intel proposed a special interface ASIC chip that would act as a translator for the SDRAMs to communicate with the chip set's RDRAM interface. The move was similar to earlier efforts to manage the transition to new memory types, such as building DIMMs with either EDO or SDRAM chips.

Yet it was a plan widely criticized by chip vendors as impractical and expensive, and even MacWilliams said he would feel no great sense of loss if it failed. "Our strategy is, number one, to make sure that the move to RDRAM volumes is smooth, rather than to make this S-RIMM," he said.

One thing S-RIMM may nonetheless have accomplished was to reinforce the idea that Intel was committed to RDRAMs. When public criticism grew its loudest, Intel opted for a contingency plan that did not call for the support of any of the competing open-industry DRAM standards, such as double-data-rate, SL-DRAM or virtual-channel memory. The latter, for example, has garnered support from forthcoming chip sets from Intel's three biggest chip-set rivals: Acer, SiS and Via Technologies.

Intel also has opted not to support a new 133-MHz SDRAM spec for main memory, which some DRAM vendors see as a natural evolutionary step. MacWilliams said there are a number of problems with that approach because it ushers in new timing requirements and may require buffers on both the motherboard and DIMMs. "Most important, it is an infrastructure change over the basic PC-100 configuration," he said.

Tolerant to alternatives
Though Intel has refused to commit to the alternative approaches, it has grown more tolerant of them. When asked about Intel's stance on alternative DRAM types at the Intel Developer's Forum last February, MacWilliams told the audience that Intel wanted to discourage the fragmentation of the DRAM architecture. Since then, Intel has changed its stance in recognition of the splintering of the PC industry and of DRAM vendors' wish to do their own thing.

"A year ago, it was Intel's responsibility to be specific for our platforms," MacWilliams said. "Vendors were asking for information and were telling us to focus on the one that mattered." But now, he said, some vendors see the offering of alternative DRAM architectures "not as fragmentation but as segmentation and providing something different. During the last year, while the mainstream technology was being focused, lots of them were content to pursue their own products for their own reasons."

As a result, while Intel is focusing its efforts on the use of RDRAMs for the performance-PC segment, it acknowledges that the cost differences and diversity of platform main-memory configurations may provide a home for different DRAM architectures. "We do look at this technology differently for every segment," MacWilliams said.

The basic PC segment will be based largely on lower-cost PC-100 SDRAMs from until at least the year 2000, in part because of the cost premium for Direct RDRAMs and because PC-100 SDRAMs are already in high volume and can be used in the same sockets as 66-MHz modules. Mobile PCs, which typically trail desktop performance, will lag the high-performance systems by about a year in the transition to Direct RDRAMs. And some segments of servers and workstations, which have traditionally achieved high bandwidth by building wide data paths, will continue down that path for some time, MacWilliams said.

Return to: TimesPeople 98