Design Methodology: Nancy Nettleton
Going to full-custom ASICs

As the ASIC methodology manager at Sun Microsystems, Nancy Nettleton is to Sun ASIC design methodology what a head umpire is to a tennis match: She has the best view of both sides of the court-design and layout-and has the ability to call fouls when appropriate. And in 1998, she has seen a few things in the IC design world that have drawn her attention.

Over the last year, Nettleton has watched the emergence of a class of designer with both ASIC and full-custom experience and has seen a growing need for designers to account for physical effects, such as IR drop and coupling, early in the process.

Nettleton oversees design methodology in a group that manages Sun's ASIC suppliers on their various technologies such as device technology, packaging and design methodology.

"Typically what happens is a Sun design group will start partitioning a system and a design manager will be given the responsibility of developing one or more ASICs," said Nettleton. "They will start specifying the ASICs and talk to us about what technologies are available to implement them. Across the whole group, we work at multiple things: the package, process technology, the voltage, the I/Os, where PLLs are, what speeds they are likely to hit . . . all of that. And we will work with them to put together a request for a quote to the suppliers. When the suppliers start quoting, we do the technology scrub to see if they can do what they say they are going to do, and if it will really work."

Nettleton hails from a small town in Idaho called Murphy and was drawn to electronics at the age of 16, when she and 89 other kids from across the state were given the chance to stay at University of Idaho for a summer hacking Fortran.

From there, Nettleton attended Case Western Reserve University in Cleveland, where she graduated in 1986 with a BS/MS in computer engineering and a BA in English.

"Computer engineering is a great degree; we studied software and hardware, did chip design and coding also," said Nettleton.

The degree and her association with other computer-engineering professionals brought her to Intel in 1987, where she worked in the central account organization in support of much of the company's processor development, from the 486 up to the Pentium Pro.

In her eight years at Intel, Nettleton moved from a CAD developer up to manager of all the in-house physical design-tool development at the company. In 1994, she took a job as CAD manager for UltraSparc II at Sun and then made the brave move to Sun's systems division to be ASIC methodology manager.

So what is a full-custom layout expert doing on the ASIC side?

According to Nettleton, with the advent of very deep-submicron design, the lines between ASIC and full-custom are blurring. She, like many of her friends from the full-custom world, have moved over to the ASIC design business.

"A lot of my buddies that worked on processor designs are now moving into semi-custom devices," said Nettleton. "The problems we used to work on in processor design are now showing up in ASIC design. It used to be there were ASICs and full-custom and there wasn't much in between. Now there is a lot in between, and it is growing. Two of my friends who were working on processors are now doing graphics chips. It's not that they have kicked their careers back-it is just that the problems they are interested in solving are manifesting themselves on those parts now."

Filling gate kinds
According to Nettleton, chief among the problems these designers are interested in is filling the large processor-like gate counts afforded by 0.18-micron process geometries.

"We are starting to see 0.18 technologies coming out. I have seen a specification for a 2.5-million-gate ASIC, not including memory. At 10 million transistors, not including memory, that is bigger, transistor-wise, than a Pentium Pro. I had a vendor present to me an outline of experiences they had doing a 7.5-million-gate ASIC-that's the size of Merced. These chips are certainly not running as fast as the processors, but still.When I look at those two things, it's not to say that the ASICs have caught up with the processors, but it is to say that the line is far more blurred than it used to be in terms of transistor speeds, raw transistor counts and the number of pads you have to solve for."

Nettleton said the new breed of designers is evolving in response to an industry that is moving from pure ASIC to customer owned tooling (COT), where instead of throwing designs over the wall to the semiconductor companies, many systems companies are doing layout in-house. Much of this layout requires the hand-tweaking skills of full-custom layout people.

"There are many, many parts that can be done as ASICs or COT, but the reason you go COT is often volume and reliability," she said, "not performance. Most design people think you go COT because you get to do much more with the design, but in reality it is much more of a business consideration. There are fairly slow parts that are going COT because they are in such high volume and there are fast parts staying in the ASIC arena because they are so low volume."

Nettleton said another reason for the emergence of semi-custom design is that physical effects such as crosstalk and IR drop have become very big issues at 0.35 and 0.25 micron.

"Designers have to look at physical stuff now-they didn't before," she said. "They have to look at layout, run Hspice, look at IR drop- and it's really not what they want to do. We are now getting ASICs that have power budgets. For the guys doing laptops that won't be a big surprise, but for system ASICs it is pretty new."

Nettleton said she recently developed a standard flow describing the hand-off from design to layout for Sun's design groups.

"I didn't used to have a standard flow for our teams, but I have been having enough trouble where I finally put one together: a vendor-generic, process technology flow, and what it almost turns out to be is a project-plan cookbook that tells you when you hand things off, what you should hand off, what gets done to it and what comes back. When I came here, I went through the different projects at Sun and there were flow problems in all of them-there were things that could have been done in the tools that could have helped them, but the other problem was just that physical design was postponed until too late in the project."

Nettleton said she is nudging Sun's design teams and requiring suppliers to work on physical design earlier in the design process.

"If you look at RTL design as a bell curve, typically physical design was started at the very tail of that bell curve. When you had your RTL 'done' and meeting timing you would do the layout. The trouble is when you start getting enough unique logic, you can do your logic in a way that it can not be physically designed correctly and you have to change both logical and physical design concurrently. You have to pull physical design forward in the process. The question is: How far do you pull it? My rule of thumb is that if a supplier has a known good design methodology, they should only have to lay the chip out twice. The design manager and the supplier both need to plan to that."

But Nettleton said she varies the methodology requirements depending on design complexity.

"If they are doing a conventional ASIC, I tell them, 'throw it over the wall and get your parasitics back and that's that,' " she said. "And unless your supplier has screwed up in your fundamental silicon correlation, you will be okay. If you get a bigger or faster part, then it depends on the supplier. If the supplier is very deep submicron ready and geared toward vertical engineering, you can still trust them, but you have to incorporate physical earlier. Then there are most ASIC suppliers, where we look at the layout and make up the difference."

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