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System-level design moves beyond RTL
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Richard Goering,
Design Automation editorial director |
The complex ASICs in the marketplace today were made possible by a shift from gate-level to register-transfer level (RTL) design. To reach the next level of complexity, EDA vendors and analysts are telling designers that another leap is necessary — from RTL to system-level design. Such a leap implies that an increasing amount of hardware design will be done using C/C++, Java, Superlog, or other high-level languages, while RTL VHDL and Verilog will be relegated to smaller blocks of timing-critical logic.
Many HDL users remain skeptical about such a shift, but as this report shows, progress is being made. The report includes arguments for C/C++ design by advocates of the CynLib C++ class library and SpecC proposal; a summary of the latest work on the System-Level Design Language (SLDL) Rosetta language; and an update on Virtual Socket Interface Alliance (VSIA) system-level standards.
Putting the rubber to the road with some real-world experiences we feature NEC describing a new system-level design methodology for ASICs; LavaLogic testing its Java-based Forge tool on a picoJava FPU core; and Lockheed making a foray into architectural modeling. Two telecom providers, Nokia and InterDigital Communications Corp., put VSIA system-level standards to the test.
On the verification front, Chameleon Systems describes its use of an RTL accelerator for hardware/software co-verification, and Cisco Systems explores transaction-based verification.
A counter-argument from verification startup Tharas Systems contends that the move from RTL isn't really needed after all.
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