NEC initiative 'ACEs' system design

By Masamichi Kawarabayashi

System-on-chip designs are expected to reach more than 30 million gates by 2002. However, conventional EDA technology is incapable of turning out ICs of that magnitude in time. But now NEC Electronics Inc. and key EDA providers have devised a significantly enhanced system-design environment, named ACE-2, that reduces SoC turnaround time.

Bridging the so-called productivity gap between silicon capacity and design throughput demands an improved SoC design methodology. In particular, advanced system-level design and a platform-based or reuse-based approach are of critical im- portance to design productivity in the SoC era.

System-level design, the development phase prior to register-transfer-level (RTL) design, is perhaps the most immature element of today's SoC development flows. Yet it is at this level where the greatest potential productivity gains can be garnered. Conceptualizing, analyzing, optimizing and verifying hardware and software implementations during early, highly abstracted design stages can go a long way toward helping designers meet tough deadlines for complex circuits.

Also helpful is a reuse-based methodology that relies on defined design content to improve designer efficiency. Bringing system-level and reuse design elements together into a cohesive SoC design methodology demands improved EDA technology and a new level of cooperation between EDA and semiconductor companies.

The three-phase ACE-2 initiative, consuming three years and $30 million, blends a combination of new EDA technologies in system analysis, hardware/software trade-offs, hardware/software design and verification, and IP modeling in an advanced SoC design methodology.

As a result of the methodological improvements in the recently completed first phase, we successfully reduced SoC design cycle time by 30 percent, from an average of 450 to 300 man-months for a typical 2-million-gate design. Later phases of the initiative are aimed at improving turnaround time by another 30 percent.

First-phase flow

The focus in the first phase was on five elements in the SoC design flow. Identified by customers as having the greatest potential impact on SoC turnaround time, they were software verification, fast RTL verification, the silicon design interface, prototyping and IP modeling. Changes made in those areas resulted in the 30 percent reduction in design turnaround time over conventional ASIC design approaches.

It is a widely accepted fact that verification is the primary bottleneck in advanced IC design. RTL simulation, widely employed to verify hardware, takes a very long time, even with the fastest RTL software simulator. Today, design complexity is increasing at such a rate that verification can now account for 50 percent to 70 percent of total design effort.

Addressing the system-verification bottleneck is very critical to meeting time-to-market, so in the first phase of ACE-2, three of the five focal areas aimed at improving verification productivity: software verification, fast RTL verification and RTL-based prototyping.

In the conventional ASIC design flow, designers verify software once a prototype sample of the target chip is available. However, to reduce design time and improve hardware/software implementation, it is highly desirable to design and verify hardware and software at the same time.

However, the difficulty with hardware/software co-verification is the slowness of RTL-based hardware simulation. The low hardware abstraction level requires the simulator to be constantly engaged and only a fraction of software can be exercised-usually only the hardware interface.

The first-phase flow deploys C/C++ abstracted models using the NitroVP tool from Cardtools Systems to improve software verification productivity in early design stages. Our software is executed on an instruction-set simulation (ISS) model with hardware models created in the NitroVP environment.

Higher C/C++ abstraction results in a somewhat less accurate hardware description, but more than 80 percent of software can be very reliably verified. The more abstract C/C++ model executes more than 100 times faster than RTL or HDL descriptions and allows repetitive, exhaustive system verification. It resolves almost all specification bugs in early design stages, much more rapidly than would be possible using RTL. It is worth noting, however, that while some engineers utilize C/C++ modeling for system description and verification tasks, it is ill-suited for hardware verification because it lacks concurrency.

Another aspect of the verification process that has plagued designers is RTL functional verification. Of particular concern is testbench creation, or the process of generating functional tests, data and temporal checking, functional coverage analysis and HDL simulation control. Testbench creation has long been the bane of IC developers seeking to verify designs. The traditional bug-detection process involves creation of a large set of vectors that ensures all lines of HDL being executed are examined. Vector generation for such exhaustive coverage requires tremendous effort. Time-consuming, largely manual processes result in protracted development schedules and inadequate coverage when applied to today's complex circuits.

In our first-phase methodology, we employ Verisity Design's Specman Elite testbench automation tools to improve RTL verification productivity. Testbench tools help deal with the problem of implementation bugs by automating test vector generation, result checking and coverage assessment.

Using an intuitive test-development language, "e," we can quickly and efficiently create a testbench and simulate an entire system much more rapidly than is possible using traditional HDL-based simulation. We can also describe check points in the testbench through temporal constructs and analyze functional coverage of the test vectors using an executable functional test plan. The Specman Elite environment also enables us to perform on-the-fly data checking for context-specific values.

We extend the utility of this rapid RTL verification technology by using the testbench tool to create processor models, a task that we previously handled with difficulty using a waveform viewer. By extracting transaction sequences that appear on the bus and comparing results with those of golden RTL, this approach makes verification much easier and enables regression tests in very little time. While that capability offers significant advantages for testbench generation and checking, it doesn't improve simulation speed itself.

The final focus of the first phase relative to verification is on early system validation. Complex embedded systems including CPU cores pose particularly difficult validation problems. Neither software simulators nor verification techniques perform sufficient validation to commit such a design to silicon. It is no longer practical to wait until a highly complex design is completely through a traditional full design and prototyping cycle to verify software and fully exercise full at-speed functionality.

To address the need for early-design, lower-risk system evaluation, we have integrated FPGA-based RTL prototyping into the flow of the first phase. Prototyping board emulation is an increasingly popular verification technique for more exhaustive validation and software development prior to committing a design to silicon. Using Synplicity Inc.'s Certify RTL prototyping environment, we automatically partition and map our design into an FPGA-based prototyping board at the RT level.

Streamlined process

With today's multimillion-gate densities and deep-submicron interconnect effects, conventional methods for physical design are inadequate. Mismatches between timing estimation in front- and back-end design stages result in iterative loops that are costly and extremely time-consuming. In the conventional physical design flow, floor planning and related analyses are performed at the gate level, making it prohibitively time consuming to iterate a design.

Consequently, very little what-if analysis and hence design optimization are possible. Even worse, such iterations, when necessary, can have devastating consequences for design schedules.

In our first-phase methodology, we have deployed new EDA technology that enables us to plan the physical design at the RT level. Using the TeraForm RTL design planner from Tera Systems Inc., we estimate and optimize area, timing and power at the RT level and control logic synthesis and place-and-route phases efficiently. By considering the physical design or silicon implementation earlier in the design cycle, we can achieve much more accurate design results in early design stages. That translates into fewer design iterations due to timing nonconvergence as well as more highly optimized designs.

IP reuse is a highly effective means of achieving productive hardware design implementation today. Reusing existing elements reduces not only design and verification costs but also design time.

Plug-and-play IP

Key to the productive use of predefined logic is a comprehensive set of IP models that plug into each stage of the design process. For each IP element in an SoC design, we need a unique model for each design phase, from system architecture exploration down to hardware verification. We compared the accuracy, execution speed and development cost associated with common models used today. The data reveal that more accuracy translates into higher development costs and lower design productivity. Therefore, in order to efficiently accomplish SoC verification tasks, it is prudent to utilize more accurate models only as necessary.

For extensive software verification, a pure C/C++ environment is essential for simulation speed with a low-level accuracy. In this case an abstracted bus model is preferred. For such tasks as verifying protocol implementation of peripheral devices attached to a system bus, the low overhead and learning curve of a standalone bus-functional model (SBFM) make it preferable to hardware-verification environments.

We create cycle-count models, ISS models and SBFMs manually with limited EDA support tools. For example, Synopsys Inc. and Mentor Graphics provide processor support packages to integrate ISS models and SBFMs into their specific EDA tools.

Managing the variety of models required to support the high number of commercially available EDA tools presents a challenge. In order to expend minimum development effort while achieving adequate accuracy and productivity, our models are portable and reusable. Portable models are executable in different tool environments, while reusability accommodates derivative models. For example, a configurable ISS of a DSP core could cover multiple derivatives for varying memory spaces as well as different peripheral configurations. A portable ISS can also be used in both codesign and coverification tools with a common API. We have developed several models based on this approach and found it practical.

Although many EDA solutions have emerged to address the goals of our initiative, much of the EDA technology that will provide critical productivity gains is still evolving. Consequently, in devising the phases of ACE-2 we tempered our productivity goals with realistic expectations for the availability of technology to support them. This is reflected by the phased ACE-2 process. While Phase 1 of the ACE-2 initiative was aimed at improving the design flow to address the most pressing issues facing designers today, Phases 2 and 3 proactively address new areas of the design flow where design tools currently do not exist. In particular, system-level analysis including hardware/software trade-off analysis, market-based design and behavioral-level synthesis are pivotal technologies for the further reduction of design cycle time by our goal of an additional 30 percent.

A new era in IC design is dawning. Driven by productivity requirements, system-level design technology is evolving rapidly. As exemplified by the ACE-2 initiative, companies such as NEC developing highly sophisticated SoC designs are actively involved in evaluating and driving the latest in EDA technology. The partnership between IC developers and EDA technologists is key to the evolution of the right solutions for increasingly sophisticated systems.

Masamichi Kawarabayashi is Senior Engineering Manager at NEC Electronics Inc.'s Technology Foundation Group (Santa Clara, Calif.).

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