VSIA develops system-level modeling standards

By Christopher K. Lennard

The Virtual Socket Interface Alliance wants to improve the understandability and integration of the system-level design process. So it has formed the System-Level Design Development Working Group to build upon the VSIA charter to streamline the virtual-component authoring-for-reuse and system-on-chip integration processes.

VSIA standards improve comprehension by specifying common modeling terms for object interfaces and behaviors. Furthermore, they tie abstract modeling concepts into existing design practices by establishing model-refinement sequences, providing model interoperability rules such as standardized protocols and function "templates" and providing virtual-component attributes to guide validation of model-abstraction completeness and correctness.

The standards of the working group, which is known as SLD DWG, are intended to apply irrespective of executable format. To ensure broad adoption, the VSIA is working with a variety of system-level design initiatives. These include the System-Level Design Language (SLDL) committee within VHDL International (VI), which presents the Rosetta constraint-specification language; the Architectural Language Committee (ALC) of Open Verilog International (OVI), which provides the Semantic Reference Manual; the Unified Modeling Language (UML), which embeds notions of concurrency and interface protocols into a software-friendly object-oriented notation, and SystemC and SpecC, which are moving toward embedding hardware and software design notions within the C language.

However, separation of executable format from design intent, or the operational principles of the model, is not expressed in a common way among these groups. This is creating general confusion in the industry as to the roles and capabilities of the different system-initiatives. These specification efforts also face two daunting problems: Design models existing in different formats must be integrated during the SoC system-design phase, and hardware and software designers will have to understand the link from abstract system concepts to their existing design and verification processes.

The SLD DWG is doing a number of things to end the confusion. These include the VSIA Taxonomy Document, the System-Level Interface (SLIF) Behavioral Documentation Standard, a performance modeling standard subgroup, an upcoming data-type standard and an embedded software development subgroup.

Levels of system design

VSIA's system-level design concept includes three basic abstractions of design refinement for an SoC — a cycle-true representation of the chip, a cycle-approximate model abstraction and a behavioral abstraction.

Cycle-true is equivalent to the standard RT level description of a component, permitting validation of the operation on a clock-cycle basis. Although accurate, this level of abstraction is extremely slow to simulate and cannot be built until the system and all its components are well defined. This is often referred to as the "implementation level" of design.

Cycle-approximate, or partially cycle accurate, implies tying actions to the concept of a "tick" but not at the granularity of clock-cycle boundaries. By allowing packetizing of data into more complex data structures and providing for partially independent execution of blocks such as through instruction set simulation to HDL cosimulation, faster simulation is made possible by trading against clock-cycle accuracy. Not all architectural elements need to be defined in detail so assembly of this abstraction can occur earlier in the design process, thereby allowing a broader range of architectural exploration.

Behavioral, or functional, modeling describes the intended function of the system with minor or no architectural considerations taken into account. When used for temporal performance estimation, these models communicate asynchronously with a "delay-line" view of time providing only coarse performance assessment but allowing assessment of functional intent. Connection between objects at the behavioral level expresses the communication principle rather than implemented protocol. This layer and its early mappings are critical in the exploration of functional and architectural options.

System design as a process is the flow from the behavioral or functional description of an application, through architectural mapping and performance modeling, to cycle-accurate block assembly and verification. It must not only ensure that the design remains consistent as it is refined, but must also allow the concept of mixed-mode simulation whereby functions at any level of abstraction can be simulated together.

The guarantee of design correctness throughout system abstraction refinement can be broken into the following principles: definition of model field of use (FOU), expression of communication, expression of functionality, SoC verification and validation.

System model field of use

A field of use for any abstract virtual-component model must be supplied if it is to be used for architectural exploration. The specification of a field of use helps ensure correct model interpretation. For example, a cycle-approximate model of a core might provide high delay accuracy under the condition that hard interrupts occur at a low frequency relative to the clock rate, but provide a poor measure of accuracy if this assumption is violated.

To ensure that these assumptions are properly identified and comparable for virtual-component system models, the SLD DWG is engaging in two efforts: first, the VSIA taxonomy for definition of abstract model classes; second, a performance modeling subgroup examining the model-refinement process and relationship of specific architectural objects to the abstract classes. These works have received input from Alcatel, ARM, Cadence, Conexant, the European Chips and Systems Initiative (ECSI), Ericsson, ICL, IRESTE, Mentor Graphics, National Labs, Simulation Magic, ST Microelectronics and Synopsys.

The VSIA Taxonomy Document v2.0, updated from the SLD Taxonomy Document v1.0, will be released later this year. This document is a comprehensive classification of model object classes with defined abstraction attributes. Each object class is described with both internal and external interface abstraction requirements, allowing attributes of mixed-abstraction models such as bus functional ones to be easily described.

Every virtual-component model authored for reuse is to be described against the temporal, data-type, functional and structural levels of refinement. For example, temporal resolution is broken into seven levels of accuracy from partially ordered event accurate (the most coarse) through to gate-propagation accurate (the most fine). The definition of these abstractions in a virtual-component model defines its object class.

The Performance Modeling Standard subgroup is working on the use of abstract models in the design process. It defines a series of system-refinement layers, moving from static, to executable abstract, to executable estimated, to partially cycle accurate, to fully cycle accurate.

Each layer uses progressive refinement-inheriting properties, or constraints, from the previous layer. The appropriateness of any general object class from the VSIA taxonomy will be associated to this sequence of refinements. Furthermore, the performance modeling standard will directly address abstracting of the most common virtual-component architectural objects such as memories, buses, communication "patterns," microcontrollers, DSPs, dedicated hardware and real-time operating system.

Physical attributes of each of these elements are listed and associated with the system-refinement levels defined. This defines a minimal-feature accuracy for every abstract model built. This ensures both a completeness of abstract model and the ability to appropriately compare two abstract objects.

Expression of communication

The System-Level Interface (SLIF) Behavioral Documentation Standard, released in March with much public interest, provides a mechanism to unify description techniques for object communication. This standard was built with input from Alcatel, Cadence, Conexant, CoWare, ICL, Mentor Graphics and Nokia.

The standard defines a common lexicon for both interface transactions and messages, such as transRead, transoftwarerite, messSense, messEmit, transOpenChannel and transCloseChannel. It introduces the concept of communication attributes such as data, control, blocking, priority, buffer, FIFO, pipeline and protocol-association. Although it borrows from many of the concepts familiar to HDL design, such as definition of ports, it generalizes the concept to cover both hardware and software descriptions as well as the expression of system-model operational assumptions. For example, in the data-flow model of computation the underlying communication principles of blocking reads and nonblocking writes are easily expressed in the format of the SLIF standard. The most important aspect of the SLIF standard is its support of hierarchical refinement of interface properties. This refinement process ensures that abstract communication properties are fully specified and shown to expand into specific protocol implementations.

The communication notions from the behavioral level, such as a FIFO write, a blocking read and a control action, are mapped to the protocol transactions of the cycle-approximate level, such as a data and address write. Then they are mapped to the clock-cycle actions at the cycle-true level. The SLIF definitions of how this refinement process is done and shown to be complete ensure consistent refinement of system properties and help to indicate how to correctly "wire" in mixed-mode simulation such as that illustrated in the figure.

Expression of functionality

The VSIA virtual-component documentation standards (SLIF and the Performance Modeling Standard) will ensure the completeness and common form for specification of the functionality and accuracy of an abstract model. Another prominent issue is data-type specification. Industry overloading of definitions for basic and fixed-point type has made C/C+-to-HDL integration, as well as behavioral-to-behavioral model integration, very difficult.

The pending SLD DWG Data-Type Standard addresses this problem. It draws from a two-year VSIA effort in alignment of C/C++ data types with the IEEE 1164 package for VHDL and, more recently, an alignment of fixed-point types with the SystemC initiative. It includes active contribution and review from Alcatel, C-Level Design, CoWare, Easics, Frontier and Synopsys.

The VSIA data-type semantics make no assumptions about compilers and run-time environments, use explicit conversion functions to avoid implicit conversions, have a string representation to serve as a foreign exchange mechanism and have defined initial values for all types. Operationally, these types are represented in C/C++ header files, but the semantics themselves may be extracted and embedded into any executable format.

The data-types and their operational classes are used at all levels of design abstraction. The SLIF standard uses these types to clearly specify type coercion and type translation operations observed at model interfaces during system refinement. During the design refinement process within system design, all properties that are refined must be back-verified against the more abstract models. As models get replaced with more accurate models or with implementations, consistency with previous executions must be checked.

Commonly, this is done through the concept of mixed-mode simulation, where more abstract (fast-executing) sections of the design drive detailed (slow but accurate) sections of the design. Although VSIA won't define strategies for mixed-mode simulation, it eases the complexity of the integration problem by providing a standard API for cycle-approximate models such as Instruction Set Simulators.

The Embedded Software Development subgroup is working on the definition of a peer-to-peer and simulation-control API for cycle-approximate, or cycle-approximate-to-cycle-accurate cosimulation. The simulation control API includes basic control for the elaboration, initialization, coordination and termination of models.

The peer-to-peer relationship defines the mechanisms for the transfer of data between models during the execution phase. A full implementation of this model is being built to validate the standard, though compliance will be specified against support of operational attributes, not adoption of the specific implementation.

The method of communication is a basic single-write mailbox semantic with multiple readers possible. This work includes key contributions from ARM, Cadence, Conexant, Infineon, Mentor Graphics and Simulation Magic.

Reviewing the road map

The SLD DWG advancements are gaining adoption faster than the standards themselves are being released. Interest in alpha and beta testing of the standards is high. The SLIF standard was alpha tested by a project within IMEC and is being beta tested by industrial projects within Alcatel, CoWare and Nokia.

The data-types standard is being alpha tested at Alcatel and multiple possible beta-test sites have expressed interest in this work. Alignment on data-types with other initiatives and standards such as SystemC and OVI is complete or progressing. The instruction set simulation API initiative has already completed alpha testing at Infineon and Conexant and several beta-test possibilities exist for this work.

The SLIF standard and SLD Taxonomy v1.0 have already been released to VSIA member companies. The VSIA Taxonomy v2.0 and Data-Types standards are expected in the third and fourth quarters and the ISS API and Performance Modeling Standards are expected toward the end of this year or early 2001.

Specifications are available to VSIA members. Nonmembers must sign a copyright license and pay an annual fee of $950 per specification, including updates.

Christopher K. Lennard is Chairman, VSIA System-Level Design Development Working Group (SLD DWG) and Senior member of consulting staff, iDesign R&D, Architecture, Cadence Design Systems (San Jose, Calif).

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