Richard Goering, Design Automation, Group Editorial Director

hip designs below 0.18 microns involves a lot more than just timing closure — designers also have to cope with signal-integrity, power, and reliability challenges. Some valuable tips for meeting these challenges are contained in the contributed articles below. They address issues such as crosstalk, IR drop, power dissipation, hot carrier injection and electromigration. They explain what causes these problems, and discuss the tools and design methodologies that can help resolve them.

Cadence Design Systems Inc. focuses on managing signal integrity throughout the design flow. A tutorial from Avanti Corp. takes a different slant by describing four issues — crosstalk noise, power dissipation, power net voltage drop, and signal and power net electromigration. Early crosstalk resolution and avoidance is the topic of a contributed piece by Monterey Design Systems Inc. Noting that signal integrity is more than just "noise," Celestry Design Technologies Inc.'s authors look at some lesser-known deep-submicron challenges, including IR drop, electromigration, hot carrier injection and negative biased temperature instability. Synopsys Inc. and Texas Instruments Inc. team up to provide a tutorial on a new methodology called static crosstalk analysis. Another real-world view comes from Aura Communications Inc., a fabless semiconductor provider of wireless personal area networks. An article from Accelerant Networks Inc. describes how the company used in-house and commercial tools to design a high-speed, mixed-signal network backplane product. And a team of authors from NEC Corp., Infineon Technologies AG, Magma Design Automation Inc. and Sequence Design Inc. show how the Advanced Library Format (ALF) reflects accurate power and signal-integrity modeling.

• Signal Integrity drives post-layout verification
  By Grego Sanguinetti

• ALF facilitates SI-aware design flow
  By Wolfgang Roethig, Vassilios Gerousis, Rajit Chandra, and Vic Kulkarni

• Early power estimates guide IP selection
  By Stephen A. Voegelin

• Crosstalk, power haunt UDSM designs
  By Bari Biswas

• Signal integrity permeates design process
  By Jim McCanny

• Deep submicron design is more than just 'noise'
  By Dale Pollek and Lifeng Wu

• IC layout must avoid crosstalk problems
  By Tak Young

• Static crosstalk analysis assures silicon success
  By Bijan Kiani and Anthony Hill