Over the 20-year history of the EDA market, numerous tool vendors have helped engineers become more productive. In the mid-1980s, for example, Mentor Graphics, Valid and Daisy Systems each created gate-level suites that allowed engineers to complete moderately complex designs. It was not, however, until three tools evolved from Cadence Design Systems Inc., Synopsys Inc. and Quad Design that the EDA industry saw its greatest leap in productivity.

Those three companies helped define the RTL tool methodology, which increased designer productivity from a peak of about 20,000 gates in 1986 to nearly 250,000 gates in the mid-1990s, essentially turbo-boosting the ASIC industry into what it is today.

Gary Smith, chief EDA analyst at DataQuest, said Cadence's Verilog XL simulator, Synopsys' Design Compiler RTL-to-gate synthesis tool and Quad's Motive static-timing tool were essential ingredients to the rise of RTL methodology. "Verilog XL established a common language to build the register-transfer level," said Smith. "Design Compiler then could take that language and translate it to gates. Motive added the exhaustive timing analysis that was lacking in Verilog XL."

Key enablers of large ASIC designs (l-r): Chuck White, Motive timing tool developer; Verilog language pioneer Phil Moorby; and Aart de Geus, for Synopsys' Design Compiler.

"Before Verilog XL and Design Compiler, ASIC design was like a sacred brotherhood filled with black-magic artists who pushed polygons around and used schematic-capture tools," said John Cooley, design consultant and head of the E-Mail Synopsys Users Group (ESNUG). "XL and Design Compiler really enabled the ASIC market, and they dumbed ASIC design down so that idiots like me and 10,000 other ESNUG members could design really big chips. At the time, you couldn't use one tool without the other," said Cooley. "The tools were and still are a lethal combination."

Synopsys' Design Compiler is largely considered the crown jewel of the RTL flow and arguably the crown jewel of the EDA industry. While numerous simulators and static-timing tools have moved in and out of the top seed since Verilog XL and Motive were introduced, Design Compiler, 14 years after its introduction, still dominates the market-share lead in logic synthesis.

Aart de Geus, chief executive officer and chairman of Synopsys, said a key to success was Synopsys' ability to "introduce a revolutionary technology that is usable in an evolutionary sense.

Optimization led to synthesis

"In hindsight, the thing we did different with Design Compiler was that we did not introduce synthesis first; what we did was introduce optimization," said de Geus. "When we introduced the tool, we took a number of designs and made them 30 percent smaller and 30 percent faster in a matter of hours. People said, 'this can't be right because I slaved over this for 30 weeks.' It would typically take a few weeks, but they would come back and say, 'I don't know how you did it, but we checked it out and it is right.'"

De Geus said Design Compiler's optimization feature got people to buy the new tool, but it took time before they trusted it enough to use the synthesis feature to translate RTL Verilog or VHDL to gates.

De Geus said the company beat out synthesis companies like Silc and Trimiter and withstood the test of time because Design Compiler optimized not only for area but also for timing.

"In the 1980s, yield started to move up to 80 or 90 percent, so area wasn't the main concern any longer for a synthesis tool-it was performance," said de Geus. "I'd argue that the timing verifier that made the biggest impact on design methodology was the one in Design Compiler."

De Geus said designers, without knowing it, also focused their design practices to use synthesis, boosting productivity. "Every single wave of a new successful methodology comes with major restrictions. The major restrictions empower automation and the automation has to be of more value than the cost of the restrictions. Design Compiler fit into that."

Looking back on Verilog XL's impact on the ASIC market, Phil Moorby, creator of the Verilog language and the Verilog XL simulator, said it was Verilog XL's speed that really differentiated it from the competition.

"The bottom line is that it was the fastest gate-level simulator out there," said Moorby. "Before we introduced XL at Gateway [now part of Cadence], designers didn't believe that simulation was useful for verification because it was too slow."

Moorby said Gateway largely bought into that notion and originally targeted XL for the test market. "We went to a customer for a benchmark and found out it was almost as fast as a Zycad hardware accelerator, which was much more expensive. We were one-third of the cost and only two or three times slower. We made it easy for design managers to justify buying the tool for verification." Moorby said another reason it did so well was because it worked so well with Design Compiler.

"In those days, we had a great relationship with Synopsys," said Moorby, noting that Cadence and Synopsys went on sales calls together.

"The thing that was so special was that the three tools work together so beautifully," said Chuck White, one of the architects of Quad Design's Motive, now vice president of electromechanical engineering at Viewlogic. "If you took any one tool out of the equation you couldn't do a large ASIC design."

"Design Compiler was and is a huge productivity tool," said White. "It was humanly possible to design a 40,000-gate design with schematics, but it would be silly to do so. Gates per engineer have gone up dramatically . . . because of Design Compiler."

"Simulation is still the only reasonable way to verify the functionality of a design," said White. "Formal verification is making inroads but it will be a long time, if ever, [before] you can specify a system with formal tools."

"If you have a half-million-gate chip, you need to prove that the chip is going to make timing," said White. "Before Motive a lot of companies used simulation for timing and got burned by corner cases. Motive didn't care about corner cases. It doesn't care if it is a one in 16 trillion event; it just proves whether or not the chip is going to work."

White said despite popular belief, Motive was not designed as pc-board tool. Rather, Larry Rubin, White and others originally designed it at Vitesse Semiconductor as a minisupercomputer verification tool. "When the rubber hit the road, Motive was at the time the only static-timing tool that could do an entire board. LSI used the tool for IC work but because the tool linked so well with the XTK cross-coupling analysis tool, it gained a great reputation in the board space as well."

Motive, which was replaced by Synopsys' PrimeTime tool as the de facto standard IC timing analysis tool, is still in use as the Viewlogic Blastfusion pc-board tool. White said in the late '80s, it didn't have an equal.

Cadence, Synopsys and Quad Design contributed tools that boosted design productivity and drove the ASIC industry to new heights in the '90s. Moving into the new millennium, the design community is again looking for EDA companies to close yet another design gap and bring design to a higher level of abstraction.

Meanwhile, companies like Cadence and CoWare, Mentor, Phil Moorby's new venture Co-design and a host of others are already gearing up to create the next productivity leap to system-level design.

The Century of the Engineer: Companies that made a difference