MANCHESTER, England — A German telecommunications company, Hagenuk GmbH, is taking steps to help ARM Ltd. add Amulet3, an asynchronous implementation of the ARM Thumb processor, become a part of ARM's portfolio of licensable cores.

The core is being developed by a team of researchers and postgraduate students at the University of Manchester, working under professor Steve Furber. Hagenuk (Kiel, Germany) appears to be planning a commercial application of Amulet3 in 1999.

"Amulet3 is likely to be the first commercial 32-bit asynchronous processor," Furber said. "This is not being built as a research prototype, it's a product prototype. It does have product application in mind and we think we'll get it into use."

Asynchronous logic does away with the clock signals of conventional logic, and uses logic modules that are self-timed and that pass results among one another using handshaking protocols. The avoidance of clocks can provide advantages in power consumption and in the RF noise characteristics of chips compared with clocked equivalents.

The development work of the Amulet3, which implements the ARM4T instruction set, is being conducted within a European collaborative research project called ATOM that is scheduled to finish its work in December. The ATOM partners include ARM, which has agreements with Manchester University that give it preferred access to technologies developed within the Amulet research group. The ATOM group also includes Hagenuk, Virata Ltd. and OptionsExist Ltd. Like ARM, the latter two companies are based in Cambridge, England.

The project is now completing the design of a chip, which includes an asynchronous RISC core and associated on-chip memories. Hagenuk is believed to be providing clocked telecommunications peripherals for the chip.

Matt Lee, responsible for European research and collaboration at ARM, declined to comment on any plans to add Amulet3 to the ARM portfolio of licensable cores. In any case, Lee said ARM's business model rests on licensing cores to semiconductor partners, rather than to OEM companies. Lee said that strong demand from an OEM could influence a semiconductor company's desire to license Amulet.

Furber said that the design of the newest version of the core, called Amulet3H, was due to be completed about the end of the year. "We have got the major job of merging our core with peripherals from elsewhere," he said. "The other half of the chip is clocked peripherals coming from a telecommunications company."

Virata said it was not the telecommunications company in question. "The core focus they are looking at is not in line with our current products, but we are always keen to learn from research results," said Chris Williams, vice president for strategic marketing at Virata:

Furber's team has done an extensive redesign of the Amulet circuitry from previous versions, dubbed Amulet1 and Amulet2E. In addition, the group has developed an on-chip asynchronous bus, called Marble (Manchester Asynchronous Bus for Low Energy), for linking other asynchronous peripherals. Marble provides a bridge to a separate clocked peripheral bus, to allow the Amulet3 core to work with conventional clocked peripherals.

VLSI Technology Inc. (San Jose, Calif.) is expected to fabricate the Amulet3H using a 0.35-micron CMOS three-layer-metal process. "It takes about three months to get silicon back," said Furber, indicating that he expects to have Amulet3H in silicon, and hopefully working, in the second quarter of 1999.

Furber said he expects Amulet3 to achieve computing performance and power efficiency similar to the ARM9 core

"We expect greater than 100 Mips," he said. "We don't have strict estimations of power consumption, but if you look at ARM7, Amulet2E and ARM9 [in terms of Mips/W] we expect to get similar results."

Although asynchronous logic can demonstrate additional benefits in power consumption over clocked versions in circumstances where processors may be halted to preserve battery life, Furber said the "easy sell" for Amulet3H would be in electromagnetic interference.

Because asynchronous chips are made from self-timed units and do not have all the circuits switching together in response to a clock signal, the RF noise generated by such chips is better than that from clocked chips, with less harmonics and smaller noise spikes.

"The more you talk to people the more you hear interference is a problem," he said. "In telecommunications and automotive electronics it's both an emissions and a susceptibility issue."

Furber said that the Amulet3 core represents an extensive redesign of the logic in Amulet2. "We have restructured it. We now have a Harvard core with separate instruction and data paths connected to a dual-ported memory," he said. "We've also enhanced the way we handle data dependencies. We use a fairly simple reorder buffer but it allows us to execute an instruction and as soon as that is complete the results are available to subsequent instructions. It's not a new idea, but fitting it into asynchronous logic was not trivial."

The team learned a great deal from the StrongARM design, he said. "That gave us the idea of building the register file with three read ports. Not many instructions require that, so it might seem like an overhead. But it does mean that instruction decode can be simplified."

A spokeswoman for Hagenuk said she was not aware of the ATOM project. The development department at Hagenuk could not be reached by press time.