PALO ALTO, Calif. — Members of the Hewlett-Packard Labs team that originally conceived the IA-64 Epic (explicitly parallel instruction computing) architecture have turned their attention to custom-configured Epic engines for embedded computing.

"We believe it is possible to start out with the high-level code for an embedded application, and compile not only machine code, but also an optimized custom wide-word machine to execute the code," said B.R. Rau, senior research scientist at the HP Labs Computer Research Center.

Such a compilation process would identify the critical paths in the code — whether they were interrupt response routines, tight inner loops or other structures — identify and make explicit the latent parallelism in the critical paths, and create an engine with sufficient hardware parallelism to meet the performance needs of the application. The resulting processing engine could then be embedded in an ASIC.

Such an approach is possible in embedded computing because embedded applications typically have a single, unchanging set of programs. Thus hardware can be optimized to the fixed set of code, rather than coming in as powerful as possible in anticipation of many different sets of programs.

Built on HP's experience in crafting the Epic architecture and its compilers, the new approach would determine just how many operations of which types could be executed in parallel, and then generate enough execution units in the processor to execute the instructions in a single cycle. Potentially, this approach could produce engines of far greater performance than would be possible with a conventional RISC processor, but with significantly fewer transistors and less complexity than would be needed for a powerful RISC CPU. Thus the approach could be applied from very high-end signal processing systems to designs of relatively low cost.

By producing a single, optimized wide-word engine, the approach would relieve designers of the often complex problem of partitioning a design between standard embedded CPUs and custom coprocessors and peripherals. Under the HP scheme, all tasks would be executed in the customized multi-execution-unit engine. In some respects this resembles the approach taken by VLIW media processor designers. But in HP's plan, a custom media processor would in effect be created for each application.

HP is reportedly already developing the compiler technology, and is experimenting with applications in such areas as an embedded Epic-powered hand-held scanner.