The point of the Triscend E5 Configurable Processor is quite specific, according to Triscend vice president of marketing Chris Balough. It is intended to be an inexpensive — $55 in hundreds for the first part, to a budgeted price under $8 for smaller parts released in the year 2000 — 8032-type microcontroller that can be field-configured to mimic nearly any 8032-derivative chip. In addition, the device has the ability to implement a wide variety of custom coprocessors on-chip, permitting it to cover a range of applications from simple 803X replacement to substitution for a modest-sized ASIC with an embedded 8032 core.

This is accomplished by combining the 8032 core with on-chip memory and two novel elements: a reusable bus and a moderate-sized, specialized PLD array.

The more obvious of these innovations is the PLD array. Not a derivative of any commercial FPGA or CPLD, the array in the E5 is configured specifically for implementing peripheral controllers and coprocessors tightly coupled to the 8032 core, said Danesh Tavana, Triscend's vice president of engineering .

Superficially the PLD is an array of relatively simple logic cells, each including a four-input look-up table and a flip-flop. The array size ranges from 512 to 3,200 cells, depending on the specific member of the E5 family. But there are additional structures in the logic array that adapt the PLD to its calling.

One type of structure is an I/O cell, built to offer the same sort of flexibility as the user I/O cells on conventional microcontrollers. In the E5 the PLD array controls most of the I/O cells, with a few dedicated to system functions, a few to the external bus and many shared with the external bus.

The PLD also contains another type of cell of a more unusual nature. These are called Selector cells. In effect, they are configurable 24-bit parallel address decoders, capable of decoding and synchronizing single-cycle read or write transactions for the rest of the PLD.

There is one selector for every 16 logic cells in the array, so that even a design that uses a large number of independent peripherals will not run out of selectors and have to use up logic cells for address decoding.

Two other modules on the chip work with the Turbo-8032 core and the PLD array to implement high-throughput designs. One is an address mapper. This device maps the three small address spaces used by the 8032 core into a single, flat address space of up to 16 Mbytes for use in the rest of the chip. The second device is a dual-channel fast DMA unit that supervises transfers between the external bus, the PLD array and the on-chip memory. This ability to move considerable amounts of data at great speed makes it practical to implement coprocessors — for signal processing, for example — that operate at throughputs well beyond the range of the 8032 core.

The E5 family will begin with a midrange part, the TE520, with 40 kbytes of on-chip SRAM, 2,048 logic cells and as many as 251 user I/O pins. That part, not yet in silicon, is scheduled to sample before the end of the year. By mid-1999 the family will include devices from 8 kbytes and 512 logic cells to 64 kbytes and 3,200 logic cells, with up to 315 user I/O pins in the largest device.

The E5 family, however, is just the beginning of Triscend's plans. The company has in the works a device based on an as-yet-undisclosed 32-bit core, with similar on-chip facilities. That is where the reusable bus comes into play.

Anticipating a family that would eventually include a selection of processor cores, Triscend developed a reusable bus not unlike the proposals from the Virtual Socket Interface alliance's on-chip-bus working group. The underlying bus design is reused, while hardware sockets adapt the bus to specific processor core choices. Thus, the PLD array — and, more important, the design of user-created devices implemented in it — will not change when moving from one processor-core family to another.

In addition to being an interesting point product and the beginning of a potentially very flexible product line, the E5 reclaims some old but long-forgotten territory in the evolution of PLDs. In its special treatment of the bus-interface problem and its tuning specifically for implementing peripherals, the E5 logic array is reminiscent of the special-purpose bus-interface PLDs that appeared at the beginning of the CPLD era.

Those devices, like the E5 array, combined specialized bus decoders with general programmable logic. They met with very limited success, perhaps because of their complexity and their eventually being overwhelmed by the FPGA steamroller. But the concept, in the new context of on-chip programmable logic, may have a much brighter future than its predecessor.