Merced, which is due in mid-2000, will be followed in late 2001 by a previously announced processor code-named McKinley. In a presentation at the Microprocessor Forum, Stephen Smith, vice president of Intel's microprocessor products group, said that two additional IA-64 architecture devices will follow.

"We will move forward to 0.13-micron technology with a product code-named Madison," he said. The device is due around 2002. Madison, which will be aimed at high-end workstation and server applications, will be followed by an IA-64 processor code-named Deerfield. According to Smith, Deerfield will be "billed as a price/performance processor."

Smith also provided a progress report and offered a peek at some additional technical details of Merced. He reported that Merced's engineering team is proceeding towards the company's goal of shipping the chip in mid-2000.

"Merced is well underway right now," he said. "We've completed the full RTL logic design. We're in the final stages of validating that. We've worked for the last six months on timing. We're now ramping our final circuit layout, with extracted parasitics."

On the technical front, Smith presented the first block diagram of Merced to be shown by Intel in public. The high-level view contained functional blocks for instruction fetch and decode; cache; bus control; translation look-aside buffer; floating-point unit; integer unit; IA-64 control; and IA-32 control.

Merced will have three levels of cache, Smith revealed. An L0 cache will be closely tied to the execution unit. It will be backed by on-chip L1 cache. The multi-megabyte L2 cache will be housed on a separate die.

Smith also revealed that the processor will be housed in a new cartridge which will contain both the CPU and Merced's caches.

On the marketing front, Smith reemphasized Intel's intention to use Merced and its companion IA-64 architecture to plow new market territory. "With IA-64, we'll be able to go into high-end technical computing areas such as EDA verification and synthesis," he said.

While Merced garnered lots of interest at the Forum, industry analysts warned that Intel will face some challenges. Linley Gwennap, vice president of Microdesign Resources, the Forum's host, wondered whether Merced's compilers will be able to extract enough parallelism from applications software to take full advantage of the processor's architecture.

According to Intel's Smith, "We'll be able to utilize the good work in compilers that have been developed over the past 15 years. We'll hook up the compilers with the hardware."