While fixed- and floating-point DSP capabilities played a part in many of the announcements here, a session on approaches to merged CPU/DSP processors also emphasized the growing importance of DSP handling in embedded applications. The session featured papers on the Hitachi SH3-DSP, Siemens Tricore and NEC V830R.

"DSP is becoming a ubiquitous enabler-for communications, audio and video," said Jeff Bier, general manager of Berkeley Design Technology Inc., a Berkeley, Calif., consulting firm.

"It's not a question of whether you do it, it's a question of how you do it," added Jim Turley, a senior analyst for the Microprocessor Report newsletter and organizer of the event. Turley described embedded processors as "the largest, fastest-growing and most interesting," part of the semiconductor industry.

One of the more unusual announcements came from startup Triscend Corp. (Mountain View, Calif.), which detailed the E5 configurable processor architecture based on an 8052 8-bit microcontroller core and programmable logic to contain peripherals or math-handling coprocessing units.

Meanwhile, Dave Jaggar, director of ARM's design center in Austin, Texas, provided details of the next-generation ARM10 Thumb. Motorola announced two processors in the Coldfire and MCore series, and IBM unwrapped a PowerPC derivative.

Jaggar said that target applications for the ARM10 will be characterized by sophisticated user interfaces rich with graphics, voice control and synthesis, and digital video. Such systems are also likely to be networked, either wired or wirelessly, with high-bandwidth connections.

To address these applications the ARM10 has been beefed up with instruction-set enhancements, an optional single- and double-precision floating-point coprocessor and 64-bit on-chip data paths. As a result, the 32-bit processor will deliver better than 400 Mips to drive third-generation mobile cellular terminals, cable modems and consumer-information appliances.

While shooting for high performance, ARM (Cambridge, England) has not abandoned its established strategy of keeping power consumption low. The company is predicting power consumption at 600mW for the CPU plus 32-kbyte instruction and data caches.

"The move to 0.25 and 0.18 micron, and 2.5- and 1.8-V operation, is the opportunity and how to stay in the sweet spot is the challenge," said Jaggar. "To keep the area and power down, we avoided the complexity and cost of a full superscalar machine. We still achieved our performance objectives by exploiting unique features of the ARM architecture to achieve a high degree of internal parallelism from a single-issue machine."

The core is designed to deliver 400 Dhrystone 2.1 Mips at 300-MHz clock frequency, and features the option of connecting to the VFP10 vector floating-point unit capable of delivering 600 Mflops at single precision or 300-Mflops double precision. The addition of separate 32-kbyte on-chip instruction and data caches, a memory-management unit and bus interface forms the ARM1020T cached processor core.

The ARM1020T will be ready to run Windows CE and other mainstream computer and real-time operating systems. Addition of the VFP10 will enable real-time MPEG-2 decoding and 3-D graphics rendering, Jaggar said.

To keep the pipelines busy, ARM has opted for 64-bit-wide data paths to connect the caches and the coprocessor interface to the integer core.

Jaggar quoted a projected die size of 50 mm² in 0.25-micron process technology, with a power consumption of 600 mW at 1.5 V and of 1 W at 2 V. He said a 300-MHz clock frequency would be obtainable at these voltages, allowing a performance-power efficiency in excess of 650-Mips/W. Tapeout is not expected until the second quarter of 1999.

Meanwhile, Brian Branson, senior design engineer at Motorola's MCore Technology Center, announced details of the M300 family, the next generation in its low-power-consumption MCore architecture. Enhancements include numeric acceleration through the addition of a single-precision 32-bit floating-point unit and support for fast integer multiply with 16 x 16 executed in a single clock cycle and 32 x 32 multiply in two cycles. Motorola also added instruction buffering and branch-penalty reduction through branch folding. Branson quoted a 40 percent improvement in real application performance over the M200 core.

Also at the forum, IBM Microelectronics announced two steps forward in its campaign to make the PowerPC a major embedded architecture: a new generation of 400-series embedded processor cores, and a unique approach to code compression for systems constrained to small program memory or 16-bit system buses.

The new core, the PowerPC 405, was said to deliver about three times the performance of IBM's existing PowerPC 401 core. Guaranteed to operate at a minimum frequency of 200 MHz in a customer's circuit, the 405 occupies about 2 mm² and consumes about 2 mW/MHz.

The core boasts several advanced features, according to IBM senior engineer Thomas Sartorius. One is a 16 x 16-to-32-bit multiply-accumulate unit, fairly common among RISC cores these days, but unusual for the PowerPC line.

Another is the inclusion of two specialized interfaces. In addition to instruction and data caches, the 405 includes a direct interface to on-chip memory, allowing the customer to, in effect, design a local scratch pad into the processor core. A sophisticated coprocessor interface makes it possible to attach specialized computational units. One customer is using it to implement FIR filters for a disk-control application.

The second part of the IBM announcement was directed at the growing interest in code-shrinking techniques, such as those used in the ARM Thumb. Rather than defining a shrunk PowerPC instruction set, IBM developed a Huffman-like compression algorithm specifically designed to compress PowerPC machine code. It is implemented in a software compression engine and a hardware decoder.

In practice, a user would compress his code during the link-and-load process, creating an object module up to 40 percent smaller than the original code. The compression software also creates a pointer table that indicates, for every cache line in the original code, what the line's physical location is in the compressed format. At run-time, when there is an instruction cache miss, the decode hardware checks the table and determines where to find the line of compressed code to load into the cache. The line is then fetched, passed through the decompression engine and into the i-cache.

The impact on code size in program memory can range from negligible to a 40 percent reduction, depending on the code, according to Sartorius. The compression software and decoder core, collectively called CodePack Compression, may be used with any PowerPC core.